MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 371

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5.4
The CSR Receive Descriptor Active (ETH_R_DES_ACTIVE) register is a command register that should
be written to indicate the receive descriptor ring has been updated (empty receive buffers have been
produced by the driver with the E bit set).
The R_DES_ACTIVE bit in the ETH_R_DES_ACTIVE register is set when the register is written. This
is independent of the data actually written. When set, the FEC polls the receive descriptor ring and
processes receive frames, provided ETH_ECNTRL[ETHER_EN] is also set. After the FEC polls a receive
descriptor whose ownership bit is not set, the FEC clears the R_DES_ACTIVE bit and ceases receive
descriptor ring polling until the bit is set again, signifying additional descriptors have been placed into the
receive descriptor ring.
The ETH_R_DES_ACTIVE register is cleared at reset and by the clearing of the ETHER_EN bit of the
ETH_ECNTRL register.
Freescale Semiconductor
Address: Base + 0x010
EBERREN
Reset
Reset
XFUNEN
CRLEN
TBIEN
RFIEN
RBIEN
TFIEN
MIIEN
LCEN
Field
W
W
R
R
16
0
0
0
0
0
CSR Receive Descriptor Active (ETH_R_DES_ACTIVE) Register
Figure 14-5. CSR Receive Descriptor Active (ETH_R_DES_ACTIVE) Register
Transmit frame interrupt enable
Transmit buffer interrupt enable
Receive frame interrupt enable
Receive buffer interrupt enable
MII interrupt enable
Ethernet controller bus error enable
Late collision enable
Collision retry limit enable
Transmit FIFO underrun enable
17
0
0
0
0
1
18
0
0
0
0
2
Table 14-7. ETH_IMASK field descriptions (continued)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
DES_
ACTI
R_
VE
23
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
Fast Ethernet Controller (FEC)
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
14-15
15
31
0
0
0
0