MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 197

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
interrupt sources are pending before setting the IE bit in the BDLC Control Register 1. If
BDLC_DLCBSVR = 0, no interrupts are pending and the user is free to enable BDLC interrupts,
if desired.
If BDLC_DLCBSVR indicates that an interrupt is pending, the user should perform whatever
actions are necessary to clear the interrupt source before enabling the interrupts. Whether any
interrupts are pending depends primarily upon how much time passes between the exit from
loopback modes and enabling the BDLC module and the enabling of interrupts. It is a good practice
to always clear any source of interrupts before enabling interrupts on any MCU subsystem.
If any interrupts are pending (BDLC_DLCBSVR not 0), then each interrupt source should be dealt
with accordingly. After all of the interrupt sources have been dealt with, BDLC_DLCBSVR should
read 0, and the user is then free to enable BDLC interrupts.
2. Enable BDLC Interrupts
The last step in initializing the BDLC module is to enable interrupts to the CPU, if so desired. This
is done by simply setting the IE bit in the BDLC_DLCBCR1 register. Following this, the BDLC
module is ready for operating in interrupt mode. If the user chooses not to enable interrupts,
BDLC_DLCBSVR must be polled periodically to ensure that state changes in the BDLC module
are detected and dealt with appropriately.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
6-61