MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 524

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I/O Control
1
2
20.2.2
20.2.2.1
20-6
IOCONTROL_BASE
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
Pads using the STD_PU_ST register have a Schmitt trigger input; pads using the STD_PU register do not.
(0xFF40_A000)
Address: Base + 0x000
0x082–0xFFF
CONT_DS
Offset from
16BIT
Reset
Field
0x081
W
R
Register Descriptions
IO_CTL_MEM Register
1
Enables pin muxing in DRAM 16 bit mode.
0 All DRAM pads are used for DRAM functionality.
1 MDQ[31:16], MDM[3:2] and MDQS[3:2] have alternate GPIO/GPT functionality. See
CONT_DS controls the slew rate of all DRAM control pads (MCS, MA[15:0], MCK, MCK, MODT, MBA[2:0],
MCAS, MRAS, MCKE, and MWE).
000 DDR pad configuration 0
001 DDR pad configuration 1
010 DDR pad configuration 2
011 DDR pad configuration 3
100 Reserved
101 Reserved
110 DDR pad configuration 6
111 DDR pad configuration 7
Note: DDR pad configurations are defined in the MPC5125 Microcontroller Data Sheet.
0
0
0
IO_CTL_J1850_RX—J1850_RX pad control register (STD_PU_ST)
Reserved
16BIT
Figure 20-1. MEM IO Control Register (IO_CTL_MEM)
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 20-2. IO_CTL_MEM field descriptions
Table 20-1. I/O Control Memory Map
0
2
Register
CONT_DS
2
0
3
Description
0
4
Chapter 2, “System Configuration and Memory
0
5
Access
R/W
DATA_DS
Freescale Semiconductor
Access: User read/write
Reset
Value
0x18
0
6
Table
3-1.
Section/Page
20.2.2.3.2/20-8
0
7