MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 281

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.3.19 Interrupt Mask Register (INT_MASK)
The Interrupt Mask Register (INT_MASK) enables or masks interrupts corresponding to the interrupt
status bits in the INT_STATUS register.
Freescale Semiconductor
Address: Base + 0x48
VSYNC_WB
WB_PEND
LS_BF_VS
Reset
Reset
UNDRUN
PARERR
VSYNC
Field
W
W
R
R
16
0
0
0
0
0
Writeback Pending Interrupt.
If enabled, this interrupt is generated in mode 2 (the combined display and writeback mode) when a writeback
operation does not complete before the display frame parallel to it. This is considered an error. The user can
select whether to redo the writeback frame, or ignore it.
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_WB_PEND].
Lines Before VSYNC interrupt.
If enabled, this interrupt is generated at the number of lines specified by THRESHOLDS[LS_BF_VS] ahead
of the vertical front porch (FP_V).
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_LS_BF_VS].
Display parameter error interrupt.
If enabled, this interrupt is generated if the user sets incorrect display parameters.
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_PARERR].
Underrun exception interrupt.
If enabled, this interrupt is generated when the display needs data, and the output buffer filling is lower than
or equal to the OUT_BUF_LOW threshold.
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_UNDRUN].
Vertical Synchronize Interrupt for writeback operation.
If enabled, this interrupt is generated at the end of a writeback frame. Used in mode 2 and 3 only.
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_VSYN_WB].
Vertical synchronization interrupt.
If enabled, this interrupt is generated at the beginning of a frame.
This interrupt is disabled by default, and is enabled by clearing INT_MASK[M_VSYNC].
17
0
0
0
0
1
18
0
0
0
0
2
Figure 10-19. Interrupt Mask Register (INT_MASK)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 10-21. INT_STATUS field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
PEND
WB_
M_
10
26
0
0
1
LS_B
F_VS
M_
11
27
0
0
1
ERR
PAR
M_
12
28
0
0
1
Display Interface Unit (DIU)
Access: User read/write
UND
RUN
M_
13
29
0
0
1
VSYC
_WB
M_
14
30
0
0
1
SYNC
10-19
M_
15
31
V
0
0
1