MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 858

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.9
For the OTG module in device mode, the Endpoint List Address (USB_ENDPOINTLISTADDR) register
contains the address of the top of the endpoint list in system memory. Bits [10–0] of this register cannot
be modified by the system software and always return 0s when read. The memory structure referenced by
this physical memory pointer is assumed to be 64 bytes. The queue head is actually a 48-byte structure,
but must be aligned on a 64-byte boundary. However, the USB_ENDPOINTLISTADDR[EPBASE] has a
granularity of 2 KB, so in practice the queue head should be 2-KB aligned.
On the OTG module, this register is shared between the host and device mode functions. In device mode,
it is the USB_ENDPOINTLISTADDR register; in host mode, it is the USB_ASYNCLISTADDR register.
See
more information. This register is not defined in the EHCI specification.
32.2.4.10 Host Controller Embedded TT Asynchronous Buffer Status
The Host Controller Embedded TT Asynchronous Buffer Status (USB_TTCTRL) register contains
parameters for internal TT operations. This register is not used in device controller operation.
32-30
Address: Base + 0x158
Reset
Reset
EPBASE
Section 32.2.4.8, “Current Asynchronous List Address Register (USB_ASYNCLISTADDR),”
Field
W
W
R
R
16
0
0
0
Endpoint List Address (USB_ENDPOINTLISTADDR) Register
(Non-EHCI)
(USB_TTCTRL) Register
Endpoint List Address. Address of the top of the endpoint list.
Figure 32-23. Endpoint List Address (USB_ENDPOINTLISTADDR) Register
17
0
0
1
EPBASE(cont.)
18
0
0
2
Table 32-24. USB_ENDPOINTLISTADDR field descriptions
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
21
0
0
0
5
22
0
0
0
6
23
EPBASE
0
0
0
7
Description
24
8
0
0
0
25
9
0
0
0
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
for
15
31
0
0
0