MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 361

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.2
Table 14-1
modes.FECn refers to FEC1 when n = 1 and FEC2 when n = 2.
Freescale Semiconductor
FECn_RX_CLK
FECn_RX_DV/
RMII_CRS_DV
Signal Name
FECn_MDIO
FECn_MDC
FECn_CRS
FECn_COL
•
•
•
the RMII interface is enabled. The RMII_10T bit in ETH_R_CNTRL register determines the speed
of operation. The reference clock for RMII is always 50 MHz, but this clock can be divided by 10
within the RMII_10T bit of ETH_R_CNTRL register to support 10 Mbit/s operation.The PHY
must be configured accordingly.
10 Mbit/s 7-wire interface operation
The FEC support 7-wire interface used by many 10Mbit/s Ethernet transceivers.The MII_MODE
bit in the ETH_R_CNTRL register controls this functionality. If this bit is cleared, MII mode is
disabled and the 10Mbit/s 7-wire mode is enabled.
Address recognition options
Refer to the ETH_R_CNTRL register for address recognition options. Also, refer to
Section 14.6.3, “Ethernet Address Recognition,”
are promiscuous, broadcast reject, individual address hash, or exact match and multicast hash
match.
Internal loopback
Internal loopback mode is selected via the LOOP bit in the ETH_R_CNTRL register. Also, refer
to
External Signal Description (Off Chip)
Section 14.6.7, “MII Internal and External Loopback,”
describes the various FEC signals, as well as indicating which signals work in available
MII
X
X
X
X
X
X
7-wire
—
—
—
X
X
X
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-1. FEC signal Descriptions
RMII
—
—
—
X
X
X
I/O
I/O
O
I
I
I
I
Asserted—This signal is asserted upon detection of a collision and
remains asserted while the collision persists. The behavior of this
signal is not specified when in full-duplex mode.
Asserted—This signal is asserted when the transmit or receive
medium is not idle. If a collision occurs, CRS remains asserted
through the duration of the collision. In RMII mode, this signal is
presented on the FECn_RX_DV pin.
Asserted—This signal provides a timing reference to the PHY for
data transfers on the FECn_MDIO signal. FECn_MDC is a periodic
and has no maximum high or low times.
Asserted—This signal transfers control/status information
between the PHY and MAC. It transitions synchronously to
FECn_MDC. The FECn_MDIO pin is a bidirectional pin. When the
FEC operates in 10 Mbit/s 7-wire interface mode, this signal
should be connected to V
Asserted—A continuous clock that provides a timing reference for
FECn_RX_DV, FECn_RXD, and FECn_RX_ER
Asserted—When this signal is asserted, the PHY indicates a valid
nibble is present on the MII. This signal remains asserted from the
first recovered nibble of the frame through the last nibble. Assertion
of FECn_RX_DV must start no later than the SFD and excludes
any EOF.
In RMII mode, this pin also generates FECn_CRS signal.
for a detailed description. The options supported
for a detailed description.
SS
Description
.
Fast Ethernet Controller (FEC)
14-5