MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 215

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

counter to limit the maximum number of consecutive transactions that are performed by masters. When
the counter expires, the arbiter ignores the REPEAT signal and falls back to the regular arbitration scheme.
See
ACR[RPTCNT].
8.3.1.3
The ARTRY protocol is used primarily by the CPU to interrupt a transaction that hits to a modified line in
its D-cache, so that it can maintain data coherency by performing the snoop copyback. In addition, any
master and/or slave can ARTRY a transaction for whatever reason.
When an address tenure is ARTRY’d, all masters must negate their bus request signals during the cycle
after ARTRY except the master that asserted ARTRY signal. The cycle after ARTRY is called WOP
(Window Of Opportunity).
During the WOP cycle, the arbiter performs the arbitration the same way as in regular arbitration cycle,
except that the parking master policy does not apply. When the CPU asserts ARTRY, the bus is
immediately granted to the CPU to perform snoop copyback. After the completion of snoop copyback, the
arbiter grants the bus back to the master that had its transaction ARTRY’d. If ARTRY was asserted by any
other master or slave, the arbiter performs the arbitration the same way as it would perform it for a regular
arbitration cycle. The master that had its transaction ARTRYed by any master or slave except CPU is put
at the end of priority list. It can be programmed to park the bus to CPU on WOP cycle or not to park it to
any master. Refer to
ACR[WPARK].
8.3.1.4
The arbiter supports address bus parking. When no master is requesting the bus, the arbiter can grant
mastership of the bus to a specified master. This is referred to as bus parking. The parked master can skip
the bus request and assume the bus mastership directly. This reduces the access latency for parked master.
See
ACR[PARKM].
8.3.1.5
For every committed address tenure except address-only or reserved-type transactions, a data tenure is
required to complete the transaction.
In the MPC5125 system, the arbiter controls the issuing of data bus grants to a master and a slave, which
are involved in a data tenure of a previously performed address tenure.
Freescale Semiconductor
•
•
Section 8.2.1.1, “Arbiter Configuration Register (ACR),”
Section 8.2.1.1, “Arbiter Configuration Register (ACR),”
In data tenure without data streaming (master or slave or both do not support data streaming), the
arbiter guarantees that the data bus grant is asserted only when the data bus is idle.
In data tenure with data streaming (both master and slave support data streaming), the arbiter
guarantees that the data bus grant is asserted when the data bus is either idle or waiting for the last
transfer acknowledge.
Address Bus Arbitration After ARTRY
Address Bus Parking
Data Bus Arbitration
Section 8.2.1.1, “Arbiter Configuration Register (ACR),”
MPC5125 Microcontroller Reference Manual, Rev. 2
for more details about programming
for more details about ACR[APARK] and
for more detail about
CSB Arbiter and Bus Monitor
8-15