MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 994

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8.5.3.1
When necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(USB_FRINDEX register) can act as a marker. To cause a packet transfer to occur at a specific
(micro)frame number [N], DCD should interrupt on SOF during frame N-1. When
USB_FRINDEX = N – 1, the DCD must write the prime bit. The USB controller primes the isochronous
endpoint in (micro)frame N-1 so that the device controller executes delivery during (micro)frame N.
32-166
•
— #Packets Occurred > 0 AND # Packets Occurred < MULT
RX Packet Retired:
— MULT counter reaches zero.
— Non-MDATA Data PID is received
— Overflow Error:
— Packet received is > maximum packet length. [Buffer Error bit is set]
— Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]
— Fulfillment Error [Transaction Error bit is set]
— # Packets Occurred > 0 AND # Packets Occurred < MULT
— CRC Error [Transaction Error bit is set]
For TX-ISO, MULT counter can be loaded with a lesser value in the dTD
multiplier override field. If the multiplier override is zero, the MULT
counter is initialized to the Multiplier in the QH.
For ISO, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame-to-(micro)frame operation, DCD should
ensure the dTD linked-list is out ahead of the device controller by at least
two (micro)frames.
Isochronous Pipe Synchronization
Priming an endpoint towards the end of (micro)frame N-1 does not
guarantee delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N+1 if device controller does not have enough time to
complete the prime before the SOF for packet N is received.
Setup
Out
In
Table 32-96. Isochronous Endpoint Bus Response Matrix
NULL
STALL
Ignore
Stall
MPC5125 Microcontroller Reference Manual, Rev. 2
1
Packet
NULL Packet
Not Primed
STALL
Ignore
CAUTION
NOTE
NOTE
Transmit
Receive
Primed
STALL
Underflow
BS Error
N/A
N/A
2
Drop Packet
Overflow
N/A
N/A
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