MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 785

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.3.2.6
The SDHC Read Time Out (SDHC_READ_TO) register defines an interval that read data must be
returned within or a timeout error occurs. After the SDHC sends out data read command, if no data is
returned within the specified interval, the STATUS[TIME_OUT_READ] and
STATUS[READ_OP_DONE] status bits are set.
Figure 28-7
Freescale Semiconductor
Address: Base + 0x14
DATA_READ_
RESPONSE
TIME_OUT
TIME OUT
Reset
Reset
Field
Field
W
W
R
R
16
0
0
1
0
shows the SDHC_READ_TO register and
SDHC Read Time Out (SDHC_READ_TO) Register
Response Timeout. This value determines the interval which detects response timeout. The clock starts
counting when the last bit of the command is sent. The clock counts unit is MMC_SD_CLK to card.
0x01 1 clock count
0x02 2 clock counts
...
0x40 64 clock counts (default)
...
0xFF 255 clock counts
Data Read Timeout. This value determines the interval read data timeouts are detected. Check the timeout
limit of the card and clock frequency to configure this register. For safety, 0xFFFF is recommended.
The time-out clock starts counting when the last bit of the command is sent. The count unit is
MMC_SD_CLK/256. The maximum delay the SDHC can tolerate for a data time out relates to the card clock.
If the clock is 25 MHz and register is 0xFFFF, the maximum delay the SDHC waits is about 670 ms. If the card
does not give the data in 670 ms, the SDHC issues a data read time out error and terminates current data
read operation. This meets the SD physical layer specification, with a typical time out limit of 100 to 200 ms.
However, for some SDIO cards, the time out limit may be as long as one second. In such cases, lower the
MMC_SD_CLK frequency to accommodate the delay to 1 s. In this case, software needs to configure the
MMC_SD_CLK to about 16 MHz and set this register to 0xFFFF.
17
0
0
1
1
Figure 28-7. SDHC Read Time Out (SDHC_READ_TO) Register
18
0
0
1
2
19
0
0
1
3
Table 28-9. SDHC_READ_TO field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 28-8. SDHC_RES_TO field descriptions
20
4
0
0
1
21
0
0
1
5
DATA_READ_TIME_OUT
22
0
0
1
6
23
0
0
1
7
Description
Description
Table 28-9
24
8
0
0
1
25
9
0
0
1
describes the bit fields.
10
26
0
0
1
Secure Digital Host Controller (SDHC)
11
27
0
0
1
12
28
0
0
1
Access: User read/write
13
29
0
0
1
14
30
0
0
1
28-13
15
31
0
0
1