MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 886

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5
Host Data Structures
This section defines the interface data structures used to communicate control, status, and data between
HCD (software) and the enhanced host controller (hardware). The data structure definitions in this section
support a 32-bit memory buffer address space. The interface consists of a periodic schedule, periodic frame
list, asynchronous schedule, isochronous transaction descriptors, split-transaction isochronous transfer
descriptors, queue heads, and queue element transfer descriptors.
The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the
host controller interface. The asynchronous list is the root for all the bulk and control transfer type support.
Isochronous data streams are managed using isochronous transaction descriptors. Isochronous
split-transaction data streams are managed with split-transaction isochronous transfer descriptors. All
interrupt, control, and bulk data streams are managed via queue heads and queue element transfer
descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and
to reduce (on average) the number of memory accesses needed to execute a USB transaction.
Software must ensure that no interface data structure reachable by the EHCI host controller spans a
4K-page boundary.
The data structures defined in this section are (from the host controller’s perspective) a mix of read-only
and read/writable fields. The host controller must preserve the read-only fields on all data structure writes.
32.5.1
Periodic Frame List
Figure 32-43
shows the organization of the periodic schedule. This schedule is for all periodic transfers
(isochronous and interrupt). The periodic schedule is referenced from the operational registers space using
the USB_PERIODICLISTBASE address register and the USB_FRINDEX register. The periodic schedule
is based on an array of pointers called the Periodic Frame List. The USB_PERIODICLISTBASE address
register is combined with the USB_FRINDEX register to produce a memory pointer into the frame list.
The periodic frame list implements a sliding window of work over time.
MPC5125 Microcontroller Reference Manual, Rev. 2
32-58
Freescale Semiconductor