MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 980

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.8
The device operation transfers a request in the memory image to and from the Universal Serial Bus. Using
a set of linked list transfer descriptors, pointed to by a queue head, the device controller performs the data
transfers. The following sections explain the use of the device controller from the device controller driver
(DCD) point-of-view and further describe how specific USB bus events relate to status changes in the
device controller programmer's interface.
32.8.1
After hardware reset, the USB module is disabled until the run/stop bit is set to 1. In the disabled state, the
pull-up on the USB D+ is not active, which prevents an attach event from occurring. At a minimum, it is
necessary to have the queue heads setup for endpoint zero before the device attach occurs. Shortly after
the device is enabled, a USB reset occurs followed by setup packet arriving at endpoint 0. A queue head
must be prepared so the device controller can store the incoming setup packet.
To initialize a device, software must perform these steps:
32-152
1. Set controller mode to device mode. Optionally set streaming disable in the USB_USBMODE
2. Optionally modify the USB_BURSTSIZE register.
0;11:0
1;10:0
31:12
Bit
9:8
7:0
Bit
register.
Device Operational Model
Device Controller Initialization
Reserved. Bits reserved for future use and should be set to zero.
Status. This field is used by the Device Controller to communicate individual command execution states back
to the Device Controller software. This field contains the status of the last transaction performed on this qTD.
The bit encodings are:
Bit Status Field Description
7 Active.
6 Halted.
5
3 Transaction Error.
4,2,0Reserved.
Buffer Pointer. Selects the page offset in memory for the packet buffer. Non-virtual memory systems typically
set the buffer pointers to a series of incrementing integers.
Current Offset. Offset into the 4kb buffer where the packet is to begin.
Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This
is typically used to correlate relative completion times of packets on an ISO endpoint.
Transitioning from host mode to device mode requires a device controller
reset before modifying USB_USBMODE.
Data Buffer Error.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-88. Buffer Page Pointer List
Table 32-87. dTD Token (continued)
NOTE
Description
Description
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