MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 722

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
Table 25-33
SICR[GenClk] must be cleared and the configuration of the
configuration example, the PSC sends three data words with 16-bit data in the 52 BCLK frame length. The
last 4 bits in the frame are empty (0).
25.5.2.5
The I2S transmission is similar to the soft modem mode. Therefore, the configuration is as described in
Section 25.5.2.3, “Transmitting and Receiving in Soft Modem Codec Mode.”
the I2S word transmission the FrameSync signal (LRCK) is stable for the complete data word and is the
opposite for the next one. To enable the I2S mode, the SICR[I2S] bit must be set. The SICR[SyncPol] bit
defines if the frame starts with a low LRCK signal or with a high LRCK signal. If the transmitter detects
the start condition, it starts to send the data from the TxFIFO. If the receiver detects a start condition, it
starts to write the data from the RX line to the RxFIFO. The FIFO does not provide the ability to mark the
25-44
Register
SICR
CCR
CR
CR
•
•
•
•
•
•
•
Frame
DATA
CLK
Use PSC1 as ESAI master
16-bit data, LSB first
BCLK frequency 4 MHz
FrameSync length 52 bit
Data shifted out on the rising edge of BCLK
Data transfer starts on FrameSync is active
FrameSync is active high
0x12D2_0000 Select the 16-bit Codec ESAI master mode, LSB first, DTS1 = 0
0x3303_0000 Set the FrameSync length (52 bit) and SCKL frequency
shows an example how to configure the PSC1 as ESAI master. For the slave mode, the bit
Start of Frame
Transmitting and Receiving in I2S Master Mode
Value
0x0A
0x05
Disable the Tx and Rx part for configuration if the PSC was enabled by the work before.
Enable Tx and Rx
First Data Word
Table 25-33. 16-Bit ESAI Master Mode for PSC1
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 25-48. ESAI Data Transmission
Frame Length
CCR
Setting
Last Data Word
register can be ignored. In this
The difference is that during
Until the Next
Frame Starts
Empty Data
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