MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 445

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.2.8
Figure 17-8
fields.
On an explicit sense cycle, the data sensed from the fuses is placed in this register at the conclusion of the
sense cycle. Software can recognize the conclusion of the sense cycle by the assertion of SNSD in
IIM_STAT.
17.3.2.9
The Program Protection (IIM_PREG_P) register prevents accidental fuse programming. The fuses can be
blown only when the value of this register is 0xAA. Software should only program this register to 0xAA
while actively blowing fuses. After the program operation is complete, this register should be immediately
reprogrammed to a different value.
Figure 17-9
Freescale Semiconductor
Address: Base + 0x01C
Reset
Reset
D[7:0]
A[7:0]
Field
Field
W
W
R
R
16
0
0
0
0
0
shows the bits in the Explicit Sense Data Register (IIM_SDAT).
shows the bits in the IIM_PREG_P register.
Explicit Sense Data Register (IIM_SDAT)
Program Protection (IIM_PREG_P) Register
The bottom eight bits of the address of the e-Fuse bit to be programmed or word to be sensed explicitly. The
address must be written prior to setting the PRG or ESNS_x bit in IIM_FCTL to initiate a program or sense
operation.
A[7:3] provides the least significant portion of the row address. A[2:0] select the bit position within the selected
row.
The data sensed from the fuses.
17
0
0
0
0
1
18
0
0
0
0
2
Figure 17-8. Explicit Sense Data Register (IIM_SDAT)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-9. IIM_SDAT field descriptions
Table 17-8. IIM_LA field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
Table 17-10
24
8
0
0
0
25
9
0
0
0
describes the bit fields.
10
26
0
0
0
Table 17-9
11
27
0
0
0
D[7:0]
Access: Supervisor read-only
12
28
0
0
0
describes the bit
13
29
0
0
0
14
30
IIM/Fusebox
0
0
0
15
31
17-9
0
0
0