MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 615

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Power Architecture then stores the identifier, the control bits and the data content into one of the
transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE
flag.
The MSCAN then schedules the message for transmission and signals the successful transmission of the
buffer by setting the associated TXE flag. A transmit interrupt (see
Interrupt”) is generated
In case more than one buffer is scheduled for transmission when the CAN bus becomes available for
arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization.
For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software
programs this field when the message is set up. The local priority reflects the priority of this particular
message relative to the set of messages transmitted from this node. The lowest binary value of the PRIO
field is defined to be the highest priority. The internal scheduling process takes place when the MSCAN
arbitrates for the bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message in one of the three transmit buffers. Because messages that are already in
transmission cannot be aborted, the user must request the abort by setting the corresponding abort request
bit (ABTRQ) (see
MSCAN then grants the request, if possible, by:
22.4.2.3
The received messages are stored in a five-stage input FIFO. The five message buffers are alternately
mapped into a single memory area as shown in
is exclusively associated with the MSCAN, the foreground receive buffer (RxFG) is addressable by the
Power Architecture as seen in
address area is applicable for the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or
extended), the data contents, and a time stamp, if enabled (for details, see
Acceptance
The receiver full flag (RXFIF) described in
(CANRFLG),”
received message with a matching identifier, this flag is set.
On reception, each message is checked to see if it passes the filter (see
Identifier Acceptance Control Register
After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.
2. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for details.
Freescale Semiconductor
1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register.
2. Setting the associated TXE flag to release the buffer.
3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
Filter”)
Receive Structures
signals the status of the foreground receive buffer. When the buffer contains a correctly
Section 22.3.2.9, “MSCAN Transmitter Message Abort Request
2
.
1
when TXEx is set and can drive the application software to reload the buffer.
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure
22-33. This scheme simplifies the manager software as only one
(CANIDAC)”) and in parallel, is written into the active RxBG.
Section 22.3.2.5, “MSCAN Receiver Flag Register
Figure
22-33. While the background receive buffer (RxBG)
Section 22.4.11.1, “Transmit
Section 22.3.2.12, “MSCAN
Section 22.4.3, “Identifier
(CANTARQ)”). The
MSCAN
22-37