MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 47

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

See
Freescale Semiconductor
ROM_LOC
Table 2-13
00
00
01
01
10
10
11
11
BMS is bit 26 of the reset configuration word high register (RCWHR). Its
initial value is set by the state of the EMB_AD02 pin at the release of
PORESET. ROM_LOC is set by bits 22 and 21 of the reset configuration
word high register (RCWHR). The initial values of these bits are set by the
states of the EMB_AD00 and EMB_AD01 pins at the release of PORESET.
for initial memory map values based on the EMBAD0/1 and BMS bits.
BMS
0
1
0
1
0
1
0
1
Table 2-13. Memory Map Values based on EMBAD0/1 and BMS
ROM_LOC
BOOT START
x1
x1
0x
0xFF80 0000
0x0000 0000
0x0100 0000
0x0100 0000
0x0100 0000
0x0100 0000
Table 2-12. NFCBAR[BASE_ADDR] Reset Value
0x0100 0000
0x0100 0000
MPC5125 Microcontroller Reference Manual, Rev. 2
BMS
0
1
x
0xFFFF FFFF
BOOT_STOP
0x007F FFFF
0x0100 FFFF
0x0100 FFFF
0x0100 FFFF
0x0100 FFFF
0x0100 FFFF
0x0100 FFFF
NOTE
System Configuration and Memory Map (XLBMEN + Mem Map)
BASE_ADDR
Reset Value
0xFFF
0x000
0x400
NFC_BASE_ADDR
0xFFF0 0000
0x4000 0000
0x4000 0000
0x0000 0000
0x4000 0000
0x4000 0000
0x4000 0000
0x4000 0000
NFC_STOP_ADDR
0xFFFF FFFF
0x400F FFFF
0x400F FFFF
0x000F FFFF
0x400F FFFF
0x400F FFFF
0x400F FFFF
0x400F FFFF
2-13