MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 511

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
RXAK
Field
SRW
AKF
IF
Acknowledge Cycle Falling Edge when Arbitration Lost and Addressed as Slave. Hardware sets the bit upon
the falling edge of the acknowledge cycle after arbitration has been lost and addressed as slave. In this
specific case, the interrupt (IF = 1) is really the second one set by the hardware.
on AKF.”
The software must use this bit to distinguish if the interrupt is the first one (set upon rising edge of
acknowledge cycle) or the second one (set upon falling edge of acknowledge cycle). The software should only
take action for AL and AAS if the interrupt is the second one, the traditional time for the interrupt.
0 First interrupt on rising edge of acknowledge cycle – software should not take AL and AAS action (see later
1 Second interrupt on falling edge of acknowledge – software should take AL and AAS action.
If AKF bit is set to 1 by hardware, software must clear this bit by writing it 0 in the interrupt routine.
Slave Read/Write. When set, bit indicates the R/W command bit value of the calling address sent from the
master.
Note: Bit is valid only when I
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
I
sets when one of the following events occurs:
0 No interrupt is generated.
1 An interrupt is generated under the above listed condition.
Software must clear this interrupt bit by writing it 0 in the interrupt routine.
Receive Acknowledge. SDA value during the bus cycle acknowledge bit.
If bit is low, it indicates an acknowledge signal was received after completion of 8 bits of data transmission on
the bus.
If bit is high, it means no acknowledge signal is detected at the 9th clock.
0 Acknowledge received.
1 No acknowledge received.
2
• Complete 1-Byte transfer (set at falling edge of ninth clock).
• A Rx calling address matches its own specific address in slave mode.
• Arbitration is lost.
C Interrupt. Sets when an interrupt is pending. If IEN is set, a processor interrupt request is generated. IF
section for typical software flow diagram).
and no other transfers were initiated. Checking this bit, the CPU can select slave Tx/Rx mode according
to the master command.
Table 19-8. I2C_MSRn field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
2
C is in slave mode, a complete address transfer occurred with an address match,
Description
Section 19.5.3, “Special Note
Inter-Integrated Circuit (I
19-19
2
C)