MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 805

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
CLK_DIV
SDHC_CLK
CLOCK DIVIDER
Clock prescaler
DMA
IPG_CLK
CLK_20M
IPG_CLK_S
Register
Handler
Table
Memory
Controller
FIFO
Gating
CMD
Interrupter
DAT
Interrupt
MMC_SD_CLK
DAT/CMD Transceiver
Figure 28-22. Clock Used in SDHC
To get the maximum power-saving during the operation, the SDHC bus clock pauses and resumes
according to the SDHC status. For example, when FIFO is full during the card read operation, the bus clock
is stopped if no further data is written to FIFO by card. It is resumed when user (DMA) clears FIFO empty
status; similarly, there are other conditions where SDHC stops the clock to save power.
The controller controls the rate of the host main clock and checks whether it is on or off. The clock is turned
off by setting the SDHC_STR_STP_CLK[STOP_CLK] bit and is turned on by setting the
SDHC_STR_STP_CLK[START_CLK] bit. To change the clock rate, software needs to write a new value
in the SDHC_CLK_RATE register.
28.5
Initialization Information
The host controls all communication between system and cards. Also, the host sends commands of two
types: broadcast and addressed (point-to-point) commands.
Broadcast commands are intended for all cards, such as: Go_Idle_State, Send_Op_Cond, All_send_CID,
and Set_relative_Addr. In broadcast mode, all cards are in the open-drain mode to avoid bus contention.
If the socket supports only one card, the broadcast command is similar as the point-to-point command.
After the broadcast command Set_relative_Addr is issued, all cards enter standby mode. Addressed type
commands are used from this point on. In this mode, the CMD/DAT I/O returns to push-pull mode to have
the driving capability for maximum frequency operation.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
28-33