MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 474

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.14 System External Interrupt Control Register (IPIC_SECNR)
The System External Interrupt Control Register (IPIC_SECNR), shown in
detect mode for external IRQ interrupt signals, determines whether the corresponding IRQx signal asserts
an interrupt request upon either a high-to-low change or low assertion on the pin. It also defines the IPIC
output interrupt type (int, cint, or smi) in the MIXA1–MIXA7 priority positions.
18-26
Address: Base + 0x3C
Reset
Reset
SIRQ0
Field
IRQ0
IRQ1
W
W
R
R
EDI0 EDI1
16
0
0
0
MIXB0T
IRQ0 external interrupt mask. Mask an interrupt by clearing the IPIC_SEMSR bit. An interrupt can be enabled
by setting the corresponding IPIC_SEMSR bit.
The IPIC_SEMSR can be read by the user at any time.
Note:
IRQ1 external interrupt mask.
Steer IRQ0.
0 IRQ0 is used as external interrupt request.
1 IRQ0 is used as external MCP request.
• IPIC_SEMSR bit positions are not affected by their relative priority.
• Pending register bits set by multiple interrupt events can be cleared only by clearing all unmasked events
• If an IPIC_SEMSR bit is masked at the same time the corresponding IPIC_SEPNR bit causes an interrupt
17
0
0
1
in the corresponding event register.
request to the core, the error vector is issued (if no other interrupts pending). Thus, an error vector routine
must always be included, even if it contains only an RFI instruction. The error vector cannot be masked.
Figure 18-17. System External Interrupt Control Register (IPIC_SECNR)
18
0
0
0
2
MIXB1T
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-17. IPIC_SEMSR field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
MIXA0T
25
9
0
0
0
10
26
0
0
0
MIXA1T
Figure
11
27
0
0
0
18-17, defines the edge
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
15
31
0
0
0
0