MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 614

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
22.4.2.1
Modern application layer software is built upon two fundamental assumptions:
The above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right
after the previous message is sent. This loading process lasts a finite amount of time and has to be
completed within the inter-frame sequence (IFS)
this is feasible for limited CAN bus speeds, it requires the Power Architecture to react with short latencies
to the transmit interrupt.
A double buffer scheme decouples the reloading of the transmit buffer from the actual message sending
and reduces the reactiveness requirements on the Power Architecture. Problems can arise if the sending of
a message is finished while the Power Architecture reloads the second buffer. No buffer would be ready
for transmission and the bus would be released.
At least three transmit buffers are required to meet the first of the above requirements under all
circumstances. The MSCAN has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN implements with
the local priority concept described in
22.4.2.2
The MSCAN has a triple transmit buffer scheme which allows multiple messages to be set up in advance
and achieve an optimized real-time performance. The three buffers are arranged as shown in
All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see
Section 22.3.3, “Programmer’s Model of Message
Buffer Priority Register (TBPR),”
are used for time stamping of a message, if required (see
(TSRH–TSRL)”).
To transmit a message, the Power Architecture must identify an available transmit buffer, which is
indicated by a set transmitter buffer empty (TXEx) flag (see
Register
buffer by writing to the CANTBSEL register (see
Selection
space (see
associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme
makes the handler software simpler because only one address area is applicable for the transmit process,
and the required address space is minimized.
1. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991.
22-36
•
•
Any CAN node is able to send out a stream of scheduled messages without releasing the bus
between the two messages. Such nodes arbitrate for the bus immediately after sending the previous
message and only release the bus in case of lost arbitration.
The internal message queue within any CAN node is organized so the highest priority message is
sent out first if more than one message is ready to be sent.
(CANTFLG)”). If a transmit buffer is available, the Power Architecture must set a pointer to this
(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address
Section 22.3.3, “Programmer’s Model of Message
Message Transmit Background
Transmit Structures
MPC5125 Microcontroller Reference Manual, Rev. 2
contains an 8-bit local priority field (PRIO). The remaining two bytes
Section 22.4.2.2, “Transmit Structures.”
1
to send an uninterrupted stream of messages. Even if
Section 22.3.2.11, “MSCAN Transmitter Buffer
Storage”). An additional
Section 22.3.3.5, “Time Stamp Register
Section 22.3.2.7, “MSCAN Transmitter Flag
Storage”). The algorithmic feature
Section 22.3.3.4, “Transmit
Freescale Semiconductor
Figure
22-33.