MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 648

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
23.7.15 IRQ and Status register (IRQ_STATUS)
1
2
3
23-18
Address: Base + 0x3F38
FLASH_CMD_BUSY Set if command execution is busy, cleared otherwise.
When written, this bit clears itself and the WERR_IRQ bit.
When written, this bit clears itself and the CMD_DONE_IRQ bit.
When written, this bit clears itself and the IDLE_IRQ bit.
CMD_DONE_IRQ
RESIDUE_BUSY
CMD_DONE_EN
Reset
Reset
WERR_STATUS
WERR_CLEAR
DMA_BUSY
WERR_IRQ
ECC_BUSY
WERR_EN
IDLE_IRQ
W
W
IDLE_EN
R WER
R
Field
R_IR
16
Q
0
0
0
0
CMD_
DONE
_IRQ
17
0
0
0
1
Enable bit for WERR_IRQ.
Enable bit for CMD_DONE_IRQ.
Write error interrupt. Set if an error condition is detected during a “flash read status” command. This bit
is cleared when the WERR_CLEAR bit is written.
Command done interrupt. Set if command processing is done. This bit is cleared when the
CMD_DONE_CLEAR bit is written.
Command idle interrupt. Set if command done, residue engine, ECC engine, and DMA engine are idle.
This bit is cleared when the IDLE_CLEAR bit is written.
Write error status. High if an eror condition was detected during the last “flash read status” command.
This bit is cleared when the WERR_CLEAR bit is written.
Set if the residue engine is busy, cleared otherwise.
Set if the ECC engine is busy, cleared otherwise.
Set if the DMA engine is busy, cleared otherwise.
0 Write error interrupt is disabled.
1 Write error interrupt is enabled.
0 Command done interrupt is disabled.
1 Command done interrupt is enabled.
Enable bit for command IDLE_IRQ.
0 Command idle interrupt is disabled.
1 Command idle interrupt is enabled.
Clear bit for WERR_IRQ. Writing ‘1’ to this bit clears WERR_IRQ.
_IRQ
IDLE
18
0
0
0
2
Figure 23-17. IRQ and Status register (IRQ_STATUS)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 23-18. IRQ_STATUS field descriptions
WERR
_STAT
US
20
4
0
0
0
FLASH
_BUSY
_CMD
21
1
0
0
5
DUE_
BUSY
RESI
22
0
0
0
6
BUSY
ECC_
23
0
0
0
7
DMA_
BUSY WER
Description
24
8
0
0
0
R_EN
25
9
0
0
0
CMD_
DONE
_EN
RESIDUE_
BUFF_NO
10
26
0
0
IDLE_
EN
11
27
0
0
WERR_
CLEAR
w1c
BUFF_NO
12
28
0
0
Freescale Semiconductor
ECC_
Access: User read/write
1
DONE_
CLEAR
CMD_
w1c
13
29
0
0
2
CLEAR
IDLE_
w1c
BUFF_NO
14
30
0
0
DMA_
3
15
31
0
0
0