MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 280

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Display Interface Unit (DIU)
10.3.3.17 Thresholds Register (THRESHOLDS)
The Thresholds Register (THRESHOLDS) sets threshold values related to DIU operations.
1
10.3.3.18 Interrupt Status Register (INT_STATUS)
The Interrupt Status Register (INT_STATUS) indicates the interrupt status. DIU has only one interrupt
signal. The CPU reads the INT_STATUS register to decide which exception occurred when an interrupt is
detected. The read operation also clears the register.
10-18
LS_BF_VS
OUT_BUF_LOW
Address: Base + 0x40
Address: Base + 0x44
These reserved bits are set to 1 on reset and must always be set to 1.
Reset
Reset
Reset
Reset
Field
W
W
W
W
R
R
R
R
1
1
16
16
1
1
0
0
0
0
0
0
1
1
1
17
17
0
0
1
Lines Before VSYNC Threshold. This threshold value generates the LS_BF_VS interrupt status. It sets the
number of lines ahead of the vertical front porch (FP_V) when the interrupt is generated.
Output Buffer Filling Low Threshold (in pixels). Generates the buffer underrun exception. An underrun
exception is generated if the display needs data, and the output buffer filling is lower than or equal to the
OUT_BUF_LOW threshold.
0
0
0
0
1
1
1
1
18
18
0
0
1
0
0
0
0
2
2
1
Figure 10-18. Interrupt Status Register (INT_STATUS)
Figure 10-17. Thresholds Register (THRESHOLDS)
1
19
19
0
0
1
0
0
0
0
3
3
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 10-20. THRESHOLDS field descriptions
1
20
20
4
0
0
1
4
0
0
0
0
1
21
21
0
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
8
0
0
0
0
25
25
9
0
0
9
0
0
0
0
LS_BF_VS
PEND
WB_
r1c
10
26
10
26
0
0
0
0
0
OUT_BUF_LOW
LS_B
F_VS
r1c
11
27
11
27
0
0
0
0
0
ERR
PAR
r1c
12
28
12
28
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read-only
UND
RUN
r1c
13
29
13
29
0
0
0
0
0
C_WB
VSYN
r1c
14
30
14
30
0
0
0
0
0
SYNC
r1c
15
31
15
31
V
0
0
0
0
0