MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 625

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits
due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be
read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO
(RxFG) does not take place while in sleep mode.
It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes
place while in sleep mode.
If the WUPE bit in CANCLT0 is not asserted, the MSCAN masks any activity it detects on CAN. The
RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode.The
MSCAN is able to leave sleep mode (wake up) only when:
Freescale Semiconductor
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•
CAN bus activity occurs and WUPE = 1
or
the Power Architecture clears the SLPRQ bit
The Power Architecture cannot clear the SLPRQ bit before sleep mode
(SLPRQ = 1 and SLPAK = 1) is active.After wake-up, the MSCAN waits
for 11 consecutive recessive bits to synchronize to the bus. As a
consequence, if the MSCAN is woken-up by a CAN frame, this frame is not
received. The receive message buffers (RxFG and RxBG) contain messages
if they were received before sleep mode was entered. All pending actions
are executed upon wake-up; copying of RxBG into RxFG, message aborts
and message transmissions. If the MSCAN remains in bus-off state after
sleep mode was left, it continues counting the 128 × 11 consecutive
recessive bits.
Figure 22-40. Simplified State Transitions for Entering/Leaving Sleep Mode
StartUp
CAN Activity &
SLPRQ
SLPRQ
CAN Activity &
MPC5125 Microcontroller Reference Manual, Rev. 2
CAN Activity
CAN Activity
Message
for Idle
Active
Tx/Rx
Wait
Idle
NOTE
CAN Activity
SLPRQ
(CAN Activity & WUPE) |
Sleep
(SLPAK & SLPRQ)
(CAN Activity & WUPE) |
CAN Activity
MSCAN
22-47