MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 375

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number:
MPC5125YVN400
Manufacturer:
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the read management frame operation has completed. At this time, the contents of the ETH_MII_DATA
register match the original value written, except for the data field, where contents have been replaced by
the value read from the PHY register.
If the MII_DATA register is written while frame generation is in progress, the frame contents are altered.
Software should use the MII_STATUS register and/or the MII interrupt to avoid writing to the
ETH_MII_DATA register while frame generation is in progress.
14.3.5.8
The MII Speed Control (ETH_MII_SPEED) register provides control of the MII clock (MDC pin)
frequency, allows dropping the preamble on the MII management frame, and provides observability
(intended for manufacturing test) of an internal counter used in generating the MDC clock signal.
To be compliant with the IEEE MII specification, the MII_SPEED field must be programmed with a value
that provides an MDC frequency of less than or equal to 2.5 MHz. The MII_SPEED bitfield must be set
to a non-zero value to source a read or write management frame. After the management frame is complete,
the ETH_MII_SPEED register may optionally be set to 0 to turn off the MDC. The MDC generated has a
50% duty cycle, except when the MII_SPEED bitfield is changed during operation (the change takes effect
following a rising or falling edge of MDC).
If the system clock is 25 MHz, programming the ETH_MII_SPEED register to 0x0000_0005 results in an
MDC frequency of 25 MHz × 1/(2 × 5) = 2.5 MHz.
MII_SPEED bitfield as a function of system clock frequency.
Freescale Semiconductor
DIS_PREAMBLE Asserting this bit causes preamble (32 ones) not to be prepended to the MII management frame. The MII
Address: Base + 0x044
MII_SPEED
Reset
Reset
Field
W
W
R
R
16
0
0
0
0
0
MII Speed Control (ETH_MII_SPEED) Register
17
standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
MII_SPEED controls the frequency of the MII management interface clock (MDC) relative to system clock.
A value of 0 in this field turns off the MDC and leaves it in a low-voltage state. Any non-zero value results in
the MDC frequency of 1/(mii_speed × 2) of the system clock frequency.
0
0
0
0
1
18
0
0
0
0
2
Figure 14-9. MII Speed Control (ETH_MII_SPEED) Register
19
0
0
0
0
3
Table 14-12. ETH_MII_SPEED field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
Table 14-13
23
0
0
0
0
7
Description
PREA
MBLE
DIS_
24
8
0
0
0
shows optimum values for the
25
9
0
0
0
10
26
0
0
0
MII_SPEED
11
27
0
0
0
Fast Ethernet Controller (FEC)
12
28
0
0
0
Access: User read/write
13
29
0
0
0
14
30
0
0
0
14-19
15
31
0
0
0
0

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