MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 710

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.5.1
Select the UART mode by writing the corresponding value to the PSC Control (SICR) register. The PSC
UART mode is the default mode after reset. The important registers to configure the PSC for UART mode
are:
25.5.1.1
Figure 25-39
An internal interrupt request signal is provided to notify the interrupt controller of an interrupt condition.
The output is the logical NOR of unmasked ISR bits. The interrupt level of a PSC module is programmed
in the interrupt controller.
The PSC can automatically transfer data using the DMA, rather than interrupting the core.
Table 25-27
25-32
•
•
•
•
•
•
IPB Interface to
the FIFOC
SICR
CSR
CTUR,
MR1 register — select the UART mode (parity mode, bits per character)
MR2 register — select RTS and CTS control, Stop Bit Length
CR register — enable or disable receiver and transmitter
IPB Clock
PSC in UART Mode
MCLK
briefly describes the PSC module signals.
register — select the clock source
Block Diagram and Signal Definition for UART Mode
register — select the UART mode
shows a simplified block diagram of the PSC for UART mode.
The terms assertion and negation are used to avoid confusion between
active-low and active-high signals.
CTLR
register — select the baud rate
PSC
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 25-39. PSC UART Block Diagram
Generation Unit
{CTUR:CTLR}
Clock
CSR
NOTE
Transmitter
Receiver
Control
Logic
Port
DCD
RTS
CTS
RxD
TxD
Freescale Semiconductor
External
Interface
Signals