MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 441

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.2.4
Figure 17-4
fields.
Freescale Semiconductor
PARITYE
SNSE
Field
WPE
OPE
RPE
shows the bits in the Error IRQ Mask (IIM_EMASK) register.
Error IRQ Mask (IIM_EMASK) Register
Write Protect Error. Indicates an e-Fuse program operation was attempted to a write-protected fuse bank, a
locked words, or when the value of IIM_PREG_P is not 0xAA. Assertion causes an interrupt request if WPE_M
is set in the errors IRQ mask register. This bit is automatically set by hardware and must be cleared by software
by writing 1 to it.
0 There was no write-protect error (read); no meaning (write).
1 There was a write-protect error (read); clear bit (write).
Override Protect Error. Indicates an attempt was made to override the values in an override-protected fuse bank
or a locked
bit is automatically set by hardware and must be cleared by software by writing 1 to it.
0 There was no override-protect error (read); no meaning (write).
1 There was an override-protect error (read); clear bit (write).
Read Protect Error. Indicates an attempt was made to read values from a read-protected fuse bank or SCC.
Assertion causes an interrupt request if RPE_M is set in the errors IRQ mask register. This bit is automatically
set by hardware and must be cleared by software by writing 1 to it.
0 There was no read-protect error (read); no meaning (write).
1 There was a read-protect error (read); clear bit (write).
Explicit Sense Cycle Error. Indicates that an explicit fuse sense was refused, because FBESP is set to 1 or more
than two bits of SNS_N, SNS_1, SNS_0, and PRG are asserted at the same moment. Assertion causes an
interrupt request if SNSE_M is set in the errors IRQ mask register. This bit is automatically set by hardware and
must be cleared by software by writing 1 to it.
0 There was no explicit sense error (read); no meaning (write).
1 There was an explicit sense error (read); clear bit (write).
Parity Error of Cache. Indicates that a parity error was detected in the hardware or software fuse cache.
Assertion causes an interrupt request if PARITYE_M is set in the errors IRQ mask register. This bit is
automatically set by hardware and must be cleared by software by writing 1 to it.
Parity is calculated for each fuse word when it is written into hardware cache for data correction check. Odd
parity is used across data bits. That is, if the data byte has odd number of 1, the parity bit is set to 1. When fuse
data is read, parity is calculated again. If the two parity valus are mismatched, a parity error is reported
0 There was no parity error (read); no meaning (write).
1 There was a parity error (read); clear bit (write).
words.
Assertion causes an interrupt request if OPE_M is set in the errors IRQ mask register. This
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-4. IIM_ERR field descriptions
Description
Table 17-5
describes the bit
IIM/Fusebox
17-5