MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 560

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
1
21.2.1.3.2
21-20
FIFO_Data_Word The FIFO data port. Reading from this location fetches data from the FIFO writing to this location writes data
Address: Base + 0x144
Reset value is indeterminate.
Reset
Reset
ALARM
EMPTY
FULL
Field
ERR
Field
OF
UF
W
W
R
R
16
0
0
0
0
0
LPC RX/TX FIFO Status (LPC_SCLPC_FIFOS) Register
Error. The flag bit is essentially the logical OR of UF and OF bits and can be polled to detect any FIFO error.
After clearing the offending condition, writing 1 to this bit clears the flag.
Underflow. The flag indicates the read pointer has surpassed the write pointer. FIFO was read beyond empty.
Resetting FIFO clears this condition; writing 1 to this bit clears the flag.
Overflow. The flag indicates the write pointer has surpassed the read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears the flag.
FIFO full. A full indication tracks with FIFO state.
This bit is set when the FIFO level is at or below (write)/above (read) the alarm watermark, as written
according to the LPC RX/TX FIFO Alarm (LPC_SCLPC_FIFOA) Register setting.
This bit is cleared when the FIFO level is at or above (write)/below (read) the granularity watermark, as
configured according to the LPC RX/TX FIFO Control (LPC_SCLPC_FIFOC) Register setting.
Setting this bit automatically signals the DMA engine to refill (write)/empty (read) the FIFO.
FIFO empty. An empty indication tracks with FIFO state.
into the FIFO. During normal operation, the DMA controller moves data to and from this register.
Note: Only full-word access is allowed. If all byte enables are not asserted when accessing this location, a
17
0
0
0
0
1
Figure 21-20. LPC RX/TX FIFO Status (LPC_SCLPC_FIFOS) Register
FIFO error flag is generated.
18
0
0
0
0
2
Table 21-20. LPC_SCLPC_FIFOD field descriptions
Table 21-21. LPC_SCLPC_FIFOS field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
ERR
w1c
25
9
0
0
0
w1c
UF
10
26
0
0
0
w1c
OF
11
27
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
FULL ALARM EMPTY
13
29
0
0
0
14
30
0
0
0
15
31
1
0
0