MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 218

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSB Arbiter and Bus Monitor
For transactions with a reserved transfer type, the arbiter performs as follows:
8.3.2.6
Table 8-13
For transactions with an illegal (ECIWX, ECOWX) transfer type, the arbiter performs as follows:
See the following for more information:
8.4
The following sections describe the initialization and error handling sequences for the arbiter:
8.4.1
The following initialization sequence is recommended:
8-18
1. Ends the address tenure by asserting AACK.
2. Reports on the event to AER[RES] if reporting is enabled by ATER[RES].
3. Issues a reset request, an MCP, or a regular interrupt according to AERR[RES] and AIDR[RES],
4. Updates the transaction attributes and address of AEATR and AEADR for the first error event.
1. Ends the address tenure by asserting AACK.
2. Starts data tenure and ends data tenure by asserting TEA.
3. Reports on the event in AER[ECW] if reporting is enabled by ATER[ECW].
4. Issues a reset request, an MCP, or a regular interrupt according to AERR[ECW] and AIDR[ECW],
5. Updates transaction attributes and address of AEATR and AEADR for the first error event.
•
•
•
•
•
•
•
1. Write to ACR to configure pipeline depth, address bus parking mode, global maximum repeat
if enabled by AMR[RES] and if reporting is enabled by ATER[RES].
if enabled by AMR[ECW] and if reporting is enabled by ATER[ECW].
Section 8.2.1.3, “Arbiter Transfer Error Register (ATER)”
Section 8.2.1.4, “Arbiter Event Register (AER)”
Section 8.2.1.5, “Arbiter Interrupt Definition Register (AIDR)”
Section 8.2.1.6, “Arbiter Mask Register (AMR)”
Section 8.2.1.7, “Arbiter Event Attributes Register (AEATR)”
Section 8.2.1.8, “Arbiter Event Address Register (AEADR)”
Section 8.2.1.9, “Arbiter Event Response Register (AERR)”
count, and address acknowledge wait states.
Initialization/Applications Information
shows transaction types that are defined as illegal.
Initialization Sequence
Illegal (ECIWX/ECOWX) Transaction Type
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 8-13. Illegal Transaction Type Encoding
TTYPE[0:4]
10100
11100
External control word write (ecowx)
External control word read (eciwx)
Bus Command
Freescale Semiconductor