MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 384

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.19 Descriptor Group Address 2 (ETH_GADDR2) Register
The Descriptor Group Address 2 (ETH_GADDR2) register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address. This register is
not affected by PORESET or HRESET and must be initialized.
14.3.5.20 FIFO Transmit FIFO Watermark (ETH_X_WMRK) Register
The FIFO Transmit FIFO Watermark (ETH_X_WMRK) register is programmed to control the amount of
data required in the transmit FIFO before transmission of a frame can begin. This allows minimizing
transmit latency (X_WMRK = 0X) or allows for larger bus access latency (X_WMRK = 11) due to
contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO
underrun due to contention for the system bus. The byte counts associated with the X_WMRK field may
need to be modified to match a given system requirement (worst case bus access latency by the transmit
data DMA channel).
14-28
Address: Base + 0x124
Reset
Reset
GADDR1
GADDR2
Field
Field
W
W
R
R
—
—
16
0
The ETH_GADDR1 register contains the upper 32 bits of the 64-bit hash table address used in the address
recognition process for receive frames with a multicast address. Bit 31 of ETH_GADDR1 contains hash index
bit 63. Bit 0 of ETH_GADDR1 contains hash index bit 32.
The ETH_GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address. Bit 31 of ETH_GADDR2 contains hash index bit 31. Bit
0 of ETH_GADDR2 contains hash index bit 0.
—
—
17
1
Figure 14-20. Descriptor Group Address 2 (ETH_GADDR2) Register
—
—
18
2
—
19
—
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-23. ETH_GADDR1 field descriptions
Table 14-24. ETH_GADDR2 field descriptions
—
—
20
4
—
—
21
5
—
—
22
6
—
—
23
GADDR2
GADDR2
7
Description
Description
—
—
24
8
—
—
25
9
—
—
10
26
—
—
11
27
—
—
12
28
Freescale Semiconductor
Access: User read/write
—
—
13
29
—
—
14
30
—
—
15
31