MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 574

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21-34
AD[31:0] (wr)
AD[31:0] (rd)
NOTES:
ACK can shorten the CS pulse width.
ALE can be active high or low, depending on the ale bit of the csboot/csx configuration register.
This diagram shows an active low scenario, which means the ALE bit is set to 0.
The length of the address latch and of the isolation cycle can be configured by the ALEN bit of the CSBOOT/CSX
configuration register. This diagram shows a setting of 0.
This diagram represents a wait state setting of 3.
Address Latch bit are set to zero. CS is asserted together with ALE.
LPC_CLK
ACK
R/W
ALE
CSx
OE
TS
Address
Latch
Address Tenure
MPC5125 Microcontroller Reference Manual, Rev. 2
Address
Address
Figure 21-29. Timing Diagram – Muxed Mode
Isolation
Data Tenure
Valid Write Data
Valid Read Data
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