MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 239

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1.9
The DMA Clear Interrupt Request (DMACINT) register provides a simple memory-mapped mechanism
to clear a given bit in the DMAINTH and DMAINTL registers to disable the interrupt request for a given
channel. The given value on a register write causes the corresponding bit in the DMAINTH or DMAINTL
register to be cleared. A data value of 64 to 127 (regardless of the number of implemented channels)
provides a global clear function, forcing the entire contents of the DMAINTH and DMAINTL registers to
be cleared, disabling all DMA interrupt requests. Reads of this register return all 0s. See
Table 9-12
9.2.1.10
The DMA Clear Error (DMACERR) register provides a simple memory-mapped mechanism to clear a
given bit in the DMAERRH and DMAERRL registers to disable the error condition flag for a given
channel. The given value on a register write causes the corresponding bit in the DMAERRH or
DMAERRL register to be cleared. A data value of 64 to 127 (regardless of the number of implemented
channels) provides a global clear function, forcing the entire contents of the DMAERRH and DMAERRL
registers to be cleared, clearing all channel error indicators. Reads of this register return all 0s. See
Figure 9-12
Freescale Semiconductor
Address: Base + 0x001C
Address: Base + 0x001D
CINT[6:0]
Reset
Reset
Field
W
W
R
R
for the DMACINT definition.
and
DMA Clear Interrupt Request (DMACINT)
DMA Clear Error (DMACERR)
Clear Interrupt Request
0-63
64-127 Clears all the bits in the DMAINTH and DMAINTL registers.
0
0
0
0
0
0
Table 9-13
Figure 9-11. DMA Clear Interrupt Request Register (DMACINT)
Clears the corresponding bit in the DMAINTH or DMAINTL register.
Figure 9-12. DMA Clear Error Register (DMACERR)
1
0
0
1
0
0
for the DMACERR definition.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 9-12. DMACINT field descriptions
0
0
0
0
2
2
0
0
0
0
3
3
Description
CERR[6:0]
CINT[6:0]
0
0
0
0
4
4
0
0
0
0
5
5
Direct Memory Access (DMA)
Access: User read/write
Access: User read/write
0
0
0
0
6
6
Figure 9-11
0
0
0
0
7
7
and
9-19