MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 145

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
DLOOP
TEOD
NBFS
Field
4XE
Digital Loopback Mode
This bit determines the input source the digital filter is connected to and can be used to isolate bus fault
conditions.If a fault condition has been detected on the bus, this control bit allows the programmer to
disconnect the digital filter from input from the receive pin (RXB) and connect it to the transmit output to the
pin (TXB). In this configuration, data sent from the transmit buffer should be reflected back into the receive
buffer. If no faults exist in the digital block, the fault is in the physical interface block or elsewhere on the J1850
bus.
0 No loopback. When cleared, digital filter input is connected to receive pin (J1850_RX) and the transmitter
1 Loopback. When set, digital filter input is connected to the transmitter output. The BDLC module is now in
Note: The DLOOP bit is a fault condition aid and should never be altered after the BDLC Data Register is
4X Mode Enable
This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbit/s) or in 4× mode at
41.6 kbit/s. This feature is useful for fast download of data into a J1850 node for diagnostic or factory
programming of the node. The effect of 4× receive operation on receive symbol timing boundaries is described
in
0 When cleared, the BDLC module transmits and receives at 10.4 kbit/s. Reception of a BREAK symbol
1 When set, the BDLC module is put in 4× (41.6 kbit/s) operation.
Normalization Bit Format Select
This bit controls the format of the normalization bit (NB). SAE J1850 strongly encourages the use of an active
long: 0 for In-Frame Responses containing CRC and active short, 1 for In-Frame Responses without CRC.
0 NB that is received or transmitted is a 1 when the response part of an In-Frame Response (IFR) ends with
1 NB that is received or transmitted is a 0 when the response part of an In-Frame Response (IFR) ends with
Transmit End of Data
This bit is set by the programmer to indicate the end of a message being sent by the BDLC. It appends an
8-bit CRC after completing transmission of the current byte in the Tx Shift Register followed by the EOD
symbol.If the transmit shadow register (refer to
transmit shadow register) is full when TEOD is set, the CRC byte and EOD is transmitted after the current byte
in the Tx Shift Register and the byte in the Tx Shadow Register have been transmitted. Once TEOD is set,
the transmit data register empty flag (TDRE) in the BDLC state vector register (BDLCSVR) is cleared to allow
lower priority interrupts to occur. This bit is also used to end an IFR. Bits TSIFR, TMIFR1, and TMIFR0
determine whether a CRC byte is appended before EOD transmission for IFRs.
0 The TEOD bit is automatically cleared after the first CRC bit is sent, or if an error or loss of arbitration is
1 Transmit EOD symbol
Section 6.4.2.10, “J1850 VPW Valid/Invalid Bits and Symbols.”
output is connected to the transmit pin (J1850_TX). The BDLC module is taken out of Digital Loopback
Mode and can now drive and receive from the J1850 bus normally. After writing DLOOP to zero, the BDLC
module requires the bus to be idle for a minimum of an EOF symbol time before allowing a reception of a
message. The BDLC module requires the bus to be idle for a minimum of an inter-frame separator symbol
time before allowing any message to be transmitted.
Digital Loopback Mode of operation. The transmit pin (J1850_TX) is driven low and not driven by the
transmitter output.
automatically clears this bit and sets the symbol invalid or out of range flag BDLC State Vector
Register = 0x1C).
a CRC byte. NB that is received or transmitted is a 0 when the response part of an In-Frame Response
(IFR) does not end with a CRC byte.
a CRC byte
(IFR) does not end with a CRC byte.
detected on the bus. When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC
receives back a valid EOD symbol, or an error condition or loss of arbitration occurs.
loaded for transmission. Changing DLOOP during a transmission may cause corrupted data to be
transmitted onto the J1850 network.
Table 6-6. BDLC_DLCBCR2 field descriptions (continued)
.
NB that is received or transmitted is a 1 when the response part of an In-Frame Response
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 6.4.4.1, “Protocol Architecture,”
Description
Byte Data Link Controller (BDLC)
for a description of the
6-9