MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 956

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
System software must save transfer state before setting the I-bit. This is required so it can correctly
determine what transfer progress (if any) occurred after the I-bit was set, and the host controller executed
it's final bus-transaction and cleared the active bit.
After system software has updated the S-mask and C-mask, it must reactivate the queue head. Because the
active bit and the I-bit cannot be updated with the same write, system software needs to use the following
algorithm to coherently re-activate a queue head that has been stopped using the I-bit.
Setting the halted bit inhibits the host controller from attempting to advance the queue between the time
the I-bit is cleared and the active bit is set.
32.6.11.3 Split Transaction Isochronous
Full-speed isochronous transfers are managed using the split-transaction protocol through a USB 2.0
transaction translator in a USB 2.0 hub. The host controller uses siTD data structure to support the special
requirements of isochronous split-transactions. This data structure uses the scheduling model of
isochronous TDs (see
model of iTDs) with the contiguous data feature provided by queue heads. This simple arrangement allows
a single isochronous scheduling model and adds the additional feature that all data received from the
endpoint (per split transaction) must land into a contiguous buffer.
32.6.11.3.1 Split Transaction Scheduling Mechanisms for Isochronous Transactions
Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline. As
with full- and low-speed interrupt, system software manages each transaction translator's periodic pipeline
by budgeting and scheduling exactly during which micro-frames the start-splits and complete-splits for
each full-speed isochronous endpoint occur. The requirements described in
Transaction Scheduling Mechanisms for Interrupt,”
boundary conditions supported by the EHCI periodic schedule. The S
where software can schedule start- and complete-splits (respectively). The H-Frame boundaries are
marked with a large, solid bold vertical line. The B-Frame boundaries are marked with a large, bold, and
dashed line. The bottom of the figure illustrates the relationship of an siTD to the H-Frame.
32-128
1. Set the halted bit
2. Clear the I-bit
3. Set the active bit and clear the halted bit in the same write.
back to the current qTD. If the S-mask indicates that a start-split is scheduled for the current
micro-frame, the host controller must not issue the start-split bus transaction; it must clear the
active bit.
Section 32.6.6, “Managing Isochronous Transfers Using iTDs,”
MPC5125 Microcontroller Reference Manual, Rev. 2
apply.
Figure 32-68
n
and C
illustrates the general scheduling
n
Section 32.6.11.2.1, “Split
labels indicate micro-frames
Freescale Semiconductor
for the operational