MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 914

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.5
The periodic schedule traversal is enabled or disabled via the periodic schedule enable bit in the
USB_USBCMD register. If the periodic schedule enable bit is cleared, the host controller simply does not
try to access the periodic frame list via the USB_PERIODICLISTBASE register. Likewise, when the
periodic schedule enable bit is a one, the host controller uses the USB_PERIODICLISTBASE register to
traverse the periodic schedule. The host controller does not react to modifications to the periodic schedule
enable immediately. To eliminate conflicts with split transactions, the host controller evaluates the periodic
schedule enable bit only when USB_FRINDEX[2:0] is 0b000. System software must not disable the
periodic schedule if the schedule contains an active split transaction work item that spans the 0b000
micro-frame. These work items must be removed from the schedule before the periodic schedule enable
bit is cleared. The periodic schedule status bit in the USB_USBSTS register indicates status of the periodic
schedule. System software enables (or disables) the periodic schedule by setting (or clearing) the periodic
schedule enable bit in the USB_USBCMD register. Software then can poll the periodic schedule status bit
to determine when the periodic schedule has made the desired transition. Software must not modify the
periodic schedule enable bit unless the value of the periodic schedule enable bit equals that of the periodic
schedule status bit.
The periodic schedule manages all isochronous and interrupt transfer streams. The base of the periodic
schedule is the periodic frame list. Software links schedule data structures to the periodic frame list to
produce a graph of scheduled data structures. The graph represents an appropriate sequence of transactions
on the USB.
linked directly to the periodic frame list. Interrupt transfers (managed with queue heads) and isochronous
streams with periods other than one are linked following the period-one iTD/siTDs. Interrupt queue heads
are linked into the frame list ordered by poll rate. Longer poll rates are linked first (for example, closest to
the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the end.
32-86
USB_FRINDEX[13:3]
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Periodic Schedule
Figure 32-55
Table 32-70. Operation of USB_FRINDEX and SOFV (SOF Value Register)
Current
SOFV
N+1
N+1
N+1
N+1
N+1
N+1
illustrates isochronous transfers (using iTDs and siTDs) with a period of one are
N
N
MPC5125 Microcontroller Reference Manual, Rev. 2
USB_FRINDEX[2:0]
111
000
001
010
011
100
101
110
USB_FRINDEX[13:3]
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+1
Next
SOFV
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N
Freescale Semiconductor
USB_FRINDEX[2:0]
000
001
010
011
100
101
110
111