MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 475

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.2.1.15 System Error Status Register (IPIC_SERSR)
Each bit in the System Error Status Register (IPIC_SERSR), shown in
external and an internal non-maskable error source machine check (mcp). When an error interrupt signal
is received, the interrupt controller sets the corresponding IPIC_SERSR bit.
Freescale Semiconductor
Address: Base + 0x40
Reset
Reset
MIXB0T
MIXB1T
MIXA0T
MIXA1T
Field
EDIx
W w1c
W
R
R
IRQ0 WDT
16
0
0
0
0
MIXB0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal (int,
cint, or smi) asserts its request to the core in the MIXB0 priority position.
These bits can be changed dynamically. The definition of MIXB0T is as follows:
00 int request is asserted to the core for MIXB0.
01 smi request is asserted to the core for MIXB0.
10 cint request is asserted to the core for MIXB0.
11 Reserved.
Same as MIXB0T, but for MIXB1T.
MIXA0 priority position IPIC output interrupt Type. Defines which type of the IPIC output interrupt signal (int,
cint, or smi) asserts its request to the core in the MIXB0 priority position.
These bits can be changed dynamically. The definition of MIXA0T is as follows:
00 int request is asserted to the core for MIXA0.
01 smi request is asserted to the core for MIXA0.
10 cint request is asserted to the core for MIXA0.
11 Reserved.
Same as MIXA0T, but for MIXA1T.
Each bit defines the edge detect mode for the external IRQ interrupt signals, and determines whether the
corresponding IRQx signal asserts an interrupt request upon either a high-to-low change or low assertion on
the pin. The corresponding IRQx signal asserts an interrupt request as follows:
0 Low assertion on IRQx generates an interrupt request.
1 High-to-low change on IRQx generates an interrupt request.
w1c
17
0
0
0
1
SBA
w1c
18
0
0
0
2
Figure 18-18. System Error Status Register (IPIC_SERSR)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-18. IPIC_SECNR field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
TEMP
125C
w1c
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
0
0
Figure
10
26
0
0
0
0
11
27
0
0
0
0
18-18, corresponds to an
12
28
0
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
18-27
15
31
0
0
0
0