MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 714

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on RxD, the state of
RxD is sampled. It samples each 16× clock for eight clocks, starting one-half clock after the transition
(asynchronous operation) or at the next rising edge of the bit-time clock (synchronous operation).
RxD input data is sampled on the rising edge of the programmed clock source. The LSB is received first.
Data is then transferred to a receiver holding register and RxRDY bit is set. If the character is less than
eightbits, the most significant unused bits in the receiver holding register are cleared.
If the MR1[RxRTS] bit was set to one, control the RTS line by writing to the output port register. For all
user generated commands to the UART receiver, like enable RX, disable RX, set break or read data from
the RX FIFO, set the associated RTS signal by writing the OP0 or
receiver automatically deasserts the RTS signal if the RX FIFO is full.
After the stop bit is detected, the receiver immediately looks for the next start bit.
25-36
•
•
•
SR [ORERR]
If RxD is sampled high, start bit is invalid; a valid start bit search begins again.
If RxD remains low, a valid start bit is assumed and receiver continues sampling input at 1-bit time
intervals at the theoretical center of the bit. This continues until the proper number of data bits and
parity, if any, is assembled and one stop bit is detected.
If a non-zero character is received without a stop bit (framing error) and RxD remains low for
one-half of bit period after stop bit is sampled, the receiver operates as if a new start bit were
detected. Parity error (PE), framing error (FE), overrun error (ORERR), and received break (RB)
conditions set respective error and break flags in SR at the received character boundary and are
valid only if RxRDY is set.
Receiver
Enabled
Overrun
RxRDY
Internal
Module
FFULL
Select
RTS
TxD
OP0[RTS] = 1
Manually Asserted First Time
Automatically Negated if Overrun Occurs
C1
Status
MPC5125 Microcontroller Reference Manual, Rev. 2
Data
(C1)
Figure 25-43. Timing Diagram—Receiver
C2
C3
Automatically Deasserted
when FIFO Reached the
Alarm Level
C4
C5 is
Lost
C5
OP1
register. However, the UART
Status
Data
(C2)
C6
Status
Automatically Asserted
when Ready to Receive
Data
(C3)
C6, C7, and C8 are lost
Status
Data
(C4)
Freescale Semiconductor
C7
command
Reset by
C8