MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 666

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management Control Module (PMC)
1
24.2.2
24.2.2.1
24-2
Address: Base + 0x00
PRE
DIV
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
0
0
0
0
Reset
Reset
W
W
R
R
CCM
0
0
0
0
16
0
0
0
0
0
Register Descriptions
PMC Configuration Register (PMC_PMCCR)
DSM
0
0
0
1
17
0
0
0
0
1
DDR
OFF
0
0
1
0
18
0
0
0
0
2
Figure 24-1. PMC Configuration Register (PMC_PMCCR)
CORE
OFF
19
0
0
0
0
3
0
1
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 24-2. PMC_PMCCR field descriptions
When Power Architecture core hits breakpoint, enter break mode.
When Power Architecture core initiates nap
reserved.
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: enter nap mode; do not put
DRAM in self-refresh mode during nap mode.
When Power Architecture core initiates sleep mode entry: enter sleep mode; do not put
DRAM in self-refresh mode during sleep mode.
PMC_PMCCR is cleared after return to full power mode.
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: enter nap mode; put DRAM in
self-refresh mode during nap mode.
When Power Architecture core initiates sleep mode entry: enter sleep mode; put DRAM
in self-refresh mode during sleep mode.
PMC_PMCCR is cleared after return to full power mode.
When Power Architecture core hits breakpoint: undefined, reserved.
When Power Architecture core initiates nap mode entry: undefined, reserved.
When Power Architecture core initiates sleep mode entry: enter deep sleep mode;
PMC_PMCCR is cleared after return to full power mode.
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
24
8
0
0
0
0
Description
25
9
0
0
0
0
Chapter 2, “System Configuration and Memory
1
mode or sleep
10
26
0
0
0
0
PRE
DIV
11
27
0
0
0
CCM DSM
2
12
28
0
0
0
mode entry: undefined,
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
DDR
OFF
14
30
0
0
0
CORE
OFF
15
31
0
0
0