MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 949

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Software should make the schedule as efficient as possible. What this means in this context is software
should have no more than one save-place FSTN reachable in any single frame. Two (or more, depending
on the implementation) could exist as full/low-speed footprints change with bandwidth adjustments. This
could occur, for example, when a bandwidth rebalance causes system software to move the save-place
FSTN from one poll rate level to another. During the transition, software must preserve the integrity of the
previous schedule until the new schedule is in place.
32.6.11.2.3 Tracking Split Transaction Progress for Interrupt Transfers
To correctly maintain the data stream, the host controller must be able to detect and report errors where
data is lost. For interrupt-IN transfers, data is lost when it makes it into the USB 2.0 hub, but the USB 2.0
host system is unable to get it from the USB 2.0 hub and into the system before it expires from the
transaction translator pipeline. When a lost data condition is detected, the queue is halted, thus signaling
system software to recover from the error. A data-loss condition exists when a start-split is issued,
accepted, and successfully executed by the USB 2.0 hub, but the complete-splits get unrecoverable errors
on the high-speed link or the complete-splits do not occur at the correct times. One reason complete-splits
might not occur at the right time would be due to host-induced system hold-offs that cause the host
controller to miss bus transactions because it cannot get timely access to the schedule in system memory.
The same condition can occur for an interrupt-OUT, but the result is not an endpoint halt condition.
Instead, it affects only the progress of the transfer. The queue head has the following fields to track the
progress of each split transaction. These fields are used to keep incremental state about which (and when)
portions have been executed.
32.6.11.2.4 Split Transaction Execution State Machine for Interrupt
In the following section, all references to micro-frame are in the context of a micro-frame within an
H-Frame.
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C-prog-mask. This is an 8-bit bit-vector where the host controller keeps track of which
complete-splits have been executed. Due to the nature of the transaction translator periodic
pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when
the complete-splits have not been executed in order. This can only occur due to system hold-offs
where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple
bit-vector the host controller sets as one of the C-prog-mask bits for each complete-split executed.
The bit position is determined by the micro-frame number in which the complete-split was
executed. The host controller always checks C-prog-mask before executing a complete-split
transaction. If the previous complete-splits have not been executed then it means one (or more)
have been skipped and data has potentially been lost.
FrameTag. The host controller uses his field during the complete-split portion of the split
transaction to tag the queue head with the frame number (H-Frame number) when the next
complete split must be executed.
S-bytes. This field can be used to store the number of data payload bytes sent during the start-split
(if the transaction was an OUT). The S-bytes field must be used to accumulate the data payload
bytes received during the complete-splits (for an IN).
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-121