MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 208

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSB Arbiter and Bus Monitor
8.2.1.6
The Arbiter Mask Register (AMR) is used to mask interrupts or reset requests. Setting a mask bit enables
the corresponding interrupt or reset request; clearing a bit masks it. Regular interrupts, MCP interrupts,
and reset requests can be masked by AMR.
8-8
Address: Base + 0x0014
Reset
Reset
ETEA
Field
ECW
RES
DTO
ATO
AO
W
W
R
R
16
0
0
0
0
0
Arbiter Mask Register (AMR)
Transfer error. External TEA. Detection of transfer error assertion of TEA signal by one of the slaves interrupt
definition.
0 Detection of transfer error assertion of TEA signal by one of the slaves causes a regular interrupt.
1 Detection of transfer error assertion of TEA signal by one of the slaves causes an MCP interrupt.
Reserved transfer type. Transaction with reserved transfer type interrupt definition.
0 Transaction with reserved transfer type causes a regular interrupt.
1 Transaction with reserved transfer type causes an MCP interrupt.
External control word transfer type. Transaction with external control word transfer type interrupt definition.
0 Transaction with external control word transfer type causes a regular interrupt.
1 Transaction with external control word transfer type causes an MCP interrupt.
Address only transfer type. Transaction with address only transfer type interrupt definition.
0 Transaction with address only transfer type causes a regular interrupt.
1 Transaction with address only transfer type causes an MCP interrupt.
Data time out. Data tenure time out interrupt definition.
0 Data tenure time out causes a regular interrupt.
1 Data tenure time out causes an MCP interrupt.
Address time out. Address tenure time out interrupt definition.
0 Address tenure time out causes a regular interrupt.
1 Address tenure time out causes an MCP interrupt.
17
0
0
0
0
1
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 8-6. Arbiter Mask Register (AMR)
20
4
0
0
0
0
Table 8-6. AIDR field descriptions
21
0
0
0
0
5
Figure 8-6
22
0
0
0
0
6
23
0
0
0
0
7
Description
shows the fields of AMR.
24
8
0
0
0
0
25
9
0
0
0
0
ETEA RES ECW
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
AO
13
29
0
0
0
DTO
14
30
0
0
0
ATO
15
31
0
0
0