MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 470

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.2.1.10 System External Interrupt Pending Register (IPIC_SEPNR)
Each bit in the System External Interrupt Pending Register (IPIC_SEPNR), shown in
corresponds to an external interrupt source. When an interrupt is received, the interrupt controller sets the
corresponding IPIC_SEPNR bit.
18-22
SYSDxT
SYSCxT
SYSBxT
SYSAxT
Field
SYSDx priority position IPIC output interrupt Type. Defines which type of IPIC output interrupt (int, cint, or smi)
asserts its request to the core in the SYSDx priority position. These bits cannot be changed dynamically. (to
change it, software must make sure the corresponding interrupt source is masked or it cannot happen during
the change).
The definition of SYSDxT is as follows:
00 int request is asserted to the core for SYSDx.
01 smi request is asserted to the core for SYSDx.
10 cint request is asserted to the core for SYSDx.
11 Reserved.
SYSCx priority position IPIC output interrupt Type. Defines which type of IPIC output interrupt (int, cint, or smi)
asserts its request to the core in the SYSCx priority position. These bits cannot be changed dynamically. (to
change it, software must make sure the corresponding interrupt source is masked or it cannot happen during
the change).
The definition of SYSCxT is as follows:
00 int request is asserted to the core for SYSCx.
01 smi request is asserted to the core for SYSCx.
10 cint request is asserted to the core for SYSCx.
11 Reserved.
SYSBx priority position IPIC output interrupt Type. Defines which type of IPIC output interrupt (int, cint, or smi)
asserts its request to the core in the SYSBx priority position. These bits cannot be changed dynamically. (to
change it, software must make sure the corresponding interrupt source is masked or it cannot happen during
the change).
The definition of SYSBxT is as follows:
00 int request is asserted to the core for SYSBx.
01 smi request is asserted to the core for SYSBx.
10 cint request is asserted to the core for SYSBx.
11 Reserved.
SYSAx priority position IPIC output interrupt Type. Defines which type of IPIC output interrupt (int, cint, or smi)
asserts its request to the core in the SYSAx priority position. These bits cannot be changed dynamically. (to
change it, software must make sure the corresponding interrupt source is masked or it cannot happen during
the change).
The definition of SYSAxT is as follows:
00 int request is asserted to the core for SYSAx.
01 smi request is asserted to the core for SYSAx.
10 cint request is asserted to the core for SYSAx.
11 Reserved.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-13. IPIC_SICNR field descriptions
Description
Freescale Semiconductor
Figure
18-13,