MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 499

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.1.6
A data arbitration procedure determines the relative priority of contending masters. A bus master loses
arbitration if it transmits logic 1 while another master transmits logic 0. Losing masters immediately
switch to slave-receive mode and stop driving SDA output. In this case, transition from master to slave
mode does not generate a STOP condition. A status bit is hardware set to indicate loss of arbitration.
Figure 19-7
19.2
Freescale Semiconductor
Name
SDA
SCL
Master1
Master2
SDA By
SDA By
External Signal Description
Master1
Master2
SDA
SCL By
SCL By
SCL
Arbitration
shows an example of two masters arbitrating for the I
SCL
I
I
2
2
C serial clock line, bidirectional
C serial data line, bidirectional
Figure 19-7. Timing Diagram – Arbitration Procedure
Figure 19-6. Timing Diagram–Clock Synchronization
MPC5125 Microcontroller Reference Manual, Rev. 2
Function
Table 19-2. Signal Properties
Wait State
Master 2 Loses Arbitration,
and Becomes Slave Receiver
2
C bus.
Start Counting
High Period
I/O
I/O
I/O
Inter-Integrated Circuit (I
Reset
1
1
Pull Up
Yes
Yes
19-7
2
C)