MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 691

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
MISC
Field
TC
Miscellaneous command.
000 No command.
001 No command.
010 Immediately disables receiver and puts the receiver in a known state. Use this command instead of
011 Reset transmitter. In UART mode, this bit immediately disables Tx and clears SR [TxEMP]. No other
100 Reset error status. In UART mode, this command clears ISR[RB,FE,PE,ORERR].
101 Reset break change interrupt. Clears the delta break bit, ISR[DB]. Command has no effect in codec mode.
110 Start break. Forces TxD low.
111 Stop break. Causes TxD to go high (mark) within two bit-times. Any characters in the Tx buffer are sent.
Transmitter command.
00 No action taken. Causes Tx to stay in current mode.
01 Transmitter enable. Enables operation of Tx channels. SR [TxEMP] sets. If Tx is already enabled, this
10 Transmitter disable. Terminates Tx operation and clears SR[TxEMP].
11 Reserved. Do not use.
— If Tx is enabled, it remains enabled.
— If Tx is disabled, it remains disabled.
command has no effect.
In UART Mode: TxEMP bits in SR become asserted.
In Codec Mode: Tx FIFO can be loaded while Tx is disabled, unlike in UART mode. Therefore this command
does not affect URERR behavior. It does not automatically set URERR. If no data is written to Tx FIFO,
URERR sets at the first FrameSync after Tx is enabled.
In AC97 Mode: URERR sets if Tx FIFO is empty, Tx is enabled, Rx detects a codec ready condition, and a
FrameSync occurs before samples are written to the Tx FIFO.
Note: In codec/AC97 mode, it is not possible to use the transmitter without the receiver. To transmit data only,
the receiver must be enabled.
— If a character is being sent when Tx is disabled, transmission completes before Tx becomes inactive.
— If Tx is already disabled, the command has no effect.
In UART Mode: SR[TxEMP] are negated.
In Codec Mode: SR[TxEMP] is negated.
Tx does not clear unless PSC is in remote loop-back or auto-echo mode. In codec mode, unlike UART mode,
the Tx FIFO may be loaded while Tx is disabled.
RECEIVER DISABLE when reconfiguring the receiver.
registers are altered. Because it places the transmitter in a known state, use this command instead of
TRANSMITTER DISABLE when reconfiguring the transmitter.
In codec mode, the TX prefetch register is cleared and URERR is not cleared by this soft reset. It is cleared
the same way as the Rx overflow bit, by a RESET ERROR STATUS command.
In codec mode, this command clears ISR[ORERR, URERR, DEOF, CMD_SEND, DATA_OVR,
DATA_VALID, and UNEX_RX_SLOT].
— If Tx is empty, break may be delayed as much as one bit-time.
— If Tx is active, break starts when character transmission completes.
Break is delayed until any character in Tx shift register is sent. Any character in Tx holding register is sent
after the break. Tx must be enabled for command to be accepted. This command ignores the CTS state
and has no effect in codec mode.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-10. CR field descriptions
Description
Programmable Serial Controller (PSC)
25-13