MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1006

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory Map
A-2
0x0_1800–0_1FFF
0x0_2000–0_20FF
0x0_2100–0_21FF
0x0_2200–0_22FF
0x0_2300–0_237F
0x0_2380–0_23FF
0x0_2400–0_27FF
0x0_2800–0_2FFF
0x0_3000–0_33FF
0x0_3400–0_3FFF
0x0_4000–0_43FF
0x0_4400–0_47FF
0x0_4800–0_4FFF
0x0_5000–0_50FF
0x0_5100–0_51FF
0x0_5200–0_8FFF
0x0_9000–0_9FFF
0x0_A000–0_AFFF
0x0_B000–0_BFFF
0x0_C000–0_FFFF
0x1_0000–1_01FF
0x1_0200–1_0FFF
0x1_1000–1_10FF
0x1_1100–1_11FF
0x1_1200–1_12FF
0x1_1300–1_13FF
0x1_1400–1_14FF
0x1_1500–1_15FF
0x1_1600–1_16FF
0x1_1700–1_17FF
0x1_1800–1_18FF
(0xFF40_0000)
Offset from
IMMRBAR
MPC5125 Microcontroller Reference Manual, Rev. 2, Release Candidate
Absolute offset
0xFF40_C000
0xFF40_A000
0xFF40_B000
0xFF40_1800
0xFF40_2000
0xFF40_2100
0xFF40_2200
0xFF40_2300
0xFF40_2380
0xFF40_2400
0xFF40_2800
0xFF40_3000
0xFF40_3400
0xFF40_4000
0xFF40_4400
0xFF40_4800
0xFF40_5000
0xFF40_5100
0xFF40_5200
0xFF40_9000
0xFF41_0100
0xFF41_1000
0xFF41_1100
0xFF41_1200
0xFF41_1300
0xFF41_1400
0xFF41_1500
0xFF41_1600
0xFF41_1700
0xFF41_1800
0xFF41_02--
Table A-1. MPC5125 memory map (continued)
1
Reserved
Reserved
Display Interface Unit (DIU)
Reserved
MSCAN3
MSCAN4
Reserved
Fast Ethernet Controller (FEC1)
USB ULPI1
Reserved
USB ULPI2
Reserved
Fast Ethernet Controller (FEC2)
General purpose timer (GPT2)
Secure digital host controller (SDHC2)
Reserved
Multi-port DRAM controller (MDDRC)
I/O control
IC identification module (IIM)
Reserved
LocalPlus controller (LPC)
Reserved
Programmable Serial Controller 0 (PSC0)
Programmable Serial Controller 1 (PSC1)
Programmable Serial Controller 2 (PSC2)
Programmable Serial Controller 3 (PSC3)
Programmable Serial Controller 4 (PSC4)
Programmable Serial Controller 5 (PSC5)
Programmable Serial Controller 6 (PSC6)
Programmable Serial Controller 7 (PSC7)
Programmable Serial Controller 8 (PSC8)
Region Name
Freescale Semiconductor
Chapter 10/10-1
Chapter 22/22-1
Chapter 22/22-1
Chapter 14/14-1
Chapter 32/32-1
Chapter 32/32-1
Chapter 14/14-1
Chapter 15/15-1
Chapter 28/28-1
Chapter 11/11-1
Chapter 20/20-1
Chapter 17/17-1
Chapter 21/21-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Chapter 25/25-1
Section/Page