MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 595

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
RSTATE[1:0]
WUPIE and WUPE (see
mechanism from deep sleep mode is required.
Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
TSTATE[1:0]
Address: Base + 0x09
WUPIE
CSCIE
OVRIE
RXFIE
Reset
Field
W
R
1
WUPIE
(CANRFLG)”).
Wake-Up Interrupt Enable
0 No interrupt request is generated from this event.
1 A wake-up event causes a Wake-Up interrupt request.
CAN Status Change Interrupt Enable
0 No interrupt request is generated from this event.
1 A CAN Status Change event causes an error interrupt request.
Receiver Status Change Enable. These RSTAT enable bits control the sensitivity level in which receiver state
changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue
to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves Bus-Off
10 Generate CSCIF interrupt only if the receiver enters or leaves RxErr or Bus-Off state. Discard other
11 Generate CSCIF interrupt on all state changes
Transmitter Status Change Enable. These TSTAT enable bits control the sensitivity level in which transmitter
state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves Bus-Off state. Discard other transmitter
10 Generate CSCIF interrupt only if the transmitter enters or leaves TxErr or Bus-Off state. Discard other
11 Generate CSCIF interrupt on all state changes
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receive Buffer Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
0
0
changes for generating CSCIF interrupt.
receiver state changes for generating CSCIF interrupt.
state changes for generating CSCIF interrupt.
transmitter state changes for generating CSCIF interrupt.
Figure 22-8. MSCAN Receiver Interrupt Enable Register (CANRIER)
Section 22.3.2.1, “MSCAN Control 0 Register
CSCIE
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-9. CANRIER field descriptions
0
2
RSTATE[1:0]
0
3
Description
(CANCTL0)”) must both be enabled if the recovery
0
4
TSTATE[1:0]
0
5
Section 22.3.2.5, “MSCAN Receiver
2
state. Discard other receiver state
OVRIE
Access: User read/write
0
6
RXFIE
0
7
MSCAN
22-17