MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 784

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.3.2.5
The SDHC Response Time Out (SDHC_RES_TO) register defines an interval within which a response
must be returned or a timeout error occurs. After SDHC sends out a command, if the card does not respond
within the specified interval, the STATUS[TIME_OUT_RESP] and the STATUS[END_CMD_RESP]
status bits are set.
Figure 28-6
28-12
DATA_ENABLE Data Enable. Specifies whether the current command includes a data transfer.
Address: Base + 0x10
WRITE_READ Write/Read. Specifies whether the data transfer of current command is a write or read operation
FORMAT_OF_
RESPONSE
Reset
Reset
Field
INIT
W
W
R
R
16
0
0
0
0
0
shows the SDHC_RES_TO register and
SDHC Response Time Out (SDHC_RES_TO) Register
Initialize. Specifies whether the additional 80-clock (MMC_SD_CLK) cycle prefix (to initialize the card) occurs
before every command. INIT enables/disables the additional 80-clock initialization time.
0 Disable 80 initialization clocks.
1 Enable 80 initialization clocks.
0 Read.
1 Write.
0 No data transfer included.
1 Date transfer include.
Format of Response. Sets the expected response format for current command. Refer to the SD I/O
Specification 1.0 for detail information of the response format.
000
001
010
011
1xx
17
0
0
0
0
1
Table 28-7. SDHC_CMD_DAT_CONT field descriptions (continued)
Figure 28-6. SDHC Response Time Out (SDHC_RES_TO) Register
No response for Current command.
Format R1/R5/R6 (48-bit Response with CRC7).
Format R2 (136-bit, CSD/CID read response).
Format R3/R4(48-bit Response without CRC check).
Reserved.
18
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
Table 28-8
0
0
0
0
7
Description
24
8
0
0
0
describes its bit fields.
25
9
0
0
1
10
26
RESPONSE TIME OUT
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0