MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 492

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18.3.8
Pending unmasked interrupts are presented to the core in order of priority according to
interrupt vector that allows the core to locate the interrupt service routine is made available to the core by
interrupt handler software reading IPIC_SIVCR, IPIC_SCVCR or IPIC_SMVCR. The interrupt controller
passes an interrupt vector corresponding to the highest-priority, unmasked, pending interrupt in response
to a read of IPIC_SIVCR, IPIC_SCVCR or IPIC_SMVCR.
low-order bits of the interrupt vector.
18.3.9
There are 5 non-maskable machine check interrupts (MCP), coming from the internal sources and one
programmable MCP from the external source.
18-44
Event
Mask
Bit
Bit
DDR MASK
DDR EVENT
Interrupt Vector Generation and Calculation
Machine Check Interrupts
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 18-29. DDR Interrupt Request Masking
XX Input (or
XX Event Bits)
Mask
IPIC_SIMSR
IPIC_SIPNRx
Bit
Table 18-4
(Other Unmasked Requests)
lists the encodings for the seven
Freescale Semiconductor
Table
Request to
the core
18-28. The