MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 552

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC5125YVN400
Manufacturer:
LTC
Quantity:
29
Part Number:
MPC5125YVN400
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
LocalPlus Bus Controller (LPC)
21.2.1.1.7
21.2.1.1.8
21-12
Address: Base + 0x030
Address: Base + 0x034
Reset
Reset
Reset
Reset
HC[6:0]
Field
HC7
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
0
Chip Select Holdcycle Control (LPC_CSHC) Register
Address Latch Timing (LPC_ALTR) Register
Holdcycles can be specified as 0 to 3. Holdcycles are added to the end of a Chip Select 7 write access and
occur in addition to any cycles that may already exist. These cycles provide the device additional time to latch
the data from the bus after a write operation.
00 Data is valid one LPC clock cycle after CS deassertion.
01 Data is valid two LPC clock cycle after CS deassertion.
10 Data is valid three LPC clock cycle after CS deassertion.
11 Data is valid four LPC clock cycle after CS deassertion.
Note: For a write burst transaction the data is valid a half cycle less.
Same as HC7, but for CS6–CS0/Boot.
17
17
0
0
0
0
0
0
0
0
1
1
Figure 21-8. Chip Select Holdcycle Control (LPC_CSHC) Register
18
18
1
1
0
0
0
0
2
2
Figure 21-9. Address Latch Timing (LPC_ALTR) Register
HC7
HC3
19
19
1
1
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-9. LPC_CSHC field descriptions
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
0
0
5
5
22
22
1
1
0
0
0
0
6
6
HC6
HC2
23
23
1
1
0
0
0
0
7
7
Description
ALT7 ALT6 ALT5 ALT4 ALT3 ALT2 ALT1 ALT0
24
24
8
0
0
0
0
8
0
0
0
25
25
9
0
0
0
0
9
0
0
0
10
26
10
26
1
1
0
0
0
HC5
HC1
11
27
11
27
1
1
0
0
0
12
28
12
28
0
0
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
0
14
30
14
30
1
1
0
0
0
HC4
HC0
15
31
15
31
1
1
0
0
0

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