MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 817

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 29
Software Watchdog Timer (WDT)
29.1
The Software Watchdog Timer (WDT) provides a method to recover from conditions caused by improper
software operation. For example, software may become lost due to a programming error or an electrical
problem. Also, the software may become trapped in a loop with no controlled exit.
The WDT is a down-counter that is periodically reset to a maximum count by writing a special service
sequence to the software watchdog service register (SWSRR). If the WDT decrements to 0x0000, a
software reset or a machine check processor exception (MCP) is generated. By default, the WDT is
enabled at the release of reset. The WDT can be disabled by setting the SWEN bit to 0. The SWEN bit is
in the watchdog control register (WDT_SWCRR).
29.1.1
Key features of the WDT include the following:
29.1.2
The WDT unit can operate in the following modes:
1. The system XTAL clock can be different from 33 MHz.
Freescale Semiconductor
•
•
•
•
•
•
16-bit prescaler and 16-bit down-counter
Selectable range for timeout period
Timeout delay of approximately 128 seconds maximum with a 33 MHz system XTAL clock
WDT enable/disable mode:
If the WDT is not needed, the user can disable it with software after a system reset. When it is
disabled, the watchdog counter and prescaler counter are held in a stopped state.
WDT output reset/interrupt mode:
Without periodic software servicing, the WDT times out and issues a reset or a nonmaskable MCP
interrupt
WDT prescaled/non-prescaled clock mode:
The WDT counter clock can be prescaled by programming the WDT_SWCRR[SWPR] bit that
controls the divide-by-65,536 of the WDT prescaler counter.
Introduction
Features
Modes of Operation
MPC5125 Microcontroller Reference Manual, Rev. 2
1
29-1