MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 950

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
As with asynchronous full- and low-speed endpoints, a split-transaction state machine manages the split
transaction sequence. Aside from the fields defined in the queue head for scheduling and tracking the split
transaction, the host controller calculates one internal mechanism that also manages the split transaction.
The internal calculated mechanism is:
Figure 32-67
each split transaction. The first is a single start-split transaction that occurs when the SplitXState is at
Do_Start and the single bit in cMicroFrameBit has a corresponding bit active in QH[S-mask]. The
transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller
unconditionally transitions the state to Do_Complete. Due to the available jitter in the transaction
translator pipeline, there is more than one complete-split transaction scheduled by software for the
Do_Complete state. This translates simply to the fact that there are multiple bits set in the QH[C-mask]
field.
The host controller keeps the queue head in the Do_Complete state until the split transaction is complete
(see definition below), or an error condition triggers the three-strikes-rule (for example, after the host tries
the same transaction three times, and each encounters an error, the host controller stops retrying the bus
transaction and halts the endpoint, therefore, requiring system software to detect the condition and perform
system-dependent recovery).
32-122
•
cMicroFrameBit. This is a single-bit encoding of the current micro-frame number. It is an eight-bit
value calculated by the host controller at the beginning of every micro-frame. It is calculated from
the three least significant bits of the USB_FRINDEX register, which is cMicroFrameBit = 1
shifted-left(USB_FRINDEX[2:0]). The cMicroFrameBit has at most one bit asserted that always
corresponds to the current micro-frame number. For example, if the current micro-frame is 0, then
cMicroFrameBit equals 0b0000_0001.
The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields to
determine whether the queue head is marked for a start- or complete-split transaction for the
current micro-frame.
illustrates how a complete interrupt-split transaction is managed. There are two phases to
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor