MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 180

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
6.4.6.4
As with a message transmission, this basic message reception flow can be interrupted if errors are detected
by the BDLC module. This can occur if an incorrect CRC is detected or if an invalid or out of range symbol
appears on the SAE J1850 bus. A problem can also arise if the CPU fails to service the BDLC Data
Register in a timely manner during a message reception.
6.4.6.4.1
After a message byte has been received, the CPU must service the BDLC Data Register before the next
byte is received, or the first byte is lost. If the BDLC Data Register is not serviced quickly enough, the next
byte received is written over the previous byte in the BDLC Data Register. No receiver overrun indication
is made to the CPU. If the CPU fails to service the BDLC module during the reception of an entire
message, the byte remaining in the BDLC Data Register is the last byte received (usually a CRC byte).
After a receiver overrun occurs, there is no way for the CPU to recover the lost byte(s), so the entire
message should be discarded. To prevent receiver overrun, the user should ensure that a BDLC RDRF
interrupt is serviced before the next byte can be received. When polling the BDLC_DLCBSVR register,
the user should select a polling interval that provides timely monitoring of the BDLC module.
6.4.6.4.2
If a CRC error is detected during a message reception, this is reflected in the BDLC_DLCBSVR register
once an EOD time is recognized by the BDLC module. Because all bytes of the message have been
received when this error is detected, software must ensure that all the received message bytes are
discarded.
6.4.6.4.3
If an invalid or out of range symbol, a framing error or a BREAK symbol is detected on the SAE J1850
bus during the reception of a message, the BDLC module immediately stops receiving the message and
discard any partially received byte. The symbol invalid or out of range status is immediately reflected in
the BDLC_DLCBSVR register. Following this, the BDLC module waits until the bus has been idle for a
time period equal to an EOF symbol before receiving another message. As with the CRC error, the user
should discard any partially received message if this occurs.
6.4.6.4.4
As mentioned above, if one or more IFR bytes are received following the reception of a message, the status
indicating the reception of the IFR byte(s) is indicated in the BDLC_DLCBSVR register before the EOF
is indicated. Refer to
deal with the reception of IFR bytes.
6-44
Receiving Exceptions
Receiver Overrun
CRC Error
Invalid or Out of Range Symbol
In-Frame Response to a Received Message
Section 6.4.8, “Receiving An In-Frame Response (IFR),”
MPC5125 Microcontroller Reference Manual, Rev. 2
for a description of how to
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