MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 199

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 7
CPU e300 Core Power Architecture
7.1
The following sections are contained in this chapter:
7.2
The module integrates a e300c4 processor core, which is based on and compatible with the 603e Power
Architecture-compliant microprocessor. The e300c4 core is completely embedded, as its address, data,
and control signals are not externally visible. The e300c4 core has the following features:
For additional information on the capabilities and features of the e300c4 core, refer to e300 user
documentation.
After power-on or hard reset, initial boot instructions are fetched from the LocalPlus bus, with CS0 active,
or from page 0 of NAND flash. To facilitate high speed execution, boot code is typically copied from a
flash or ROM device to SDRAM. The e300c4 core can execute code from the on-chip SRAM.
The e300c4 core has memory mapped access to all resources, including:
Freescale Semiconductor
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e300c4 Processor Core Functional Overview
e300c4 Core Reference Manual
Unsupported e300c4 Core Features
e300 Power Architecture Core
Dual Issue, superscalar architecture
32 KB instruction cache, 32 KB data cache
Double precision FPU
Instruction and data MMU
Power management modes:
— Nap
— Doze
— Sleep
Standard and critical interrupt capability
All on-chip programming registers
External SDRAM
Internal SRAM
Introduction
e300c4 Processor Core Functional Overview
MPC5125 Microcontroller Reference Manual, Rev. 2
7-1